SoC Design Verification Engineer in Ely

Job Description \n SoC Design Verification Engineer \n Job Title: SoC Design Verification Engineer/Senior Design Verification Engineer Location: Bristol & Cambridge, UK Number of Positions: 20 (10 Bristol/10 Cambridge) Contract Duration: 6 months Rate: £55 per hour (Inside IR35) Working Model: Hybrid - 3 days onsite and 2 days remote Experience: 5-20 Years Notice Period: Immediate or maximum 2 weeks \n Job Overview \n We are looking for experienced SoC Design Verification Engineers to join Synopsys Inc. for a next-generation multi-die System-on-Chip (SoC) project. \n The successful candidates will work on subsystem-level and SoC-level functional verification using SystemVerilog and UVM methodologies. The role also involves processor-based verification through Embedded C test programs running on processor cores. \n Candidates should have strong debugging skills, hands-on UVM experience and the ability to enhance and maintain existing verification environments. \n Key Responsibilities \n \n \n Perform subsystem-level and SoC-level functional verification. \n \n Develop, modify and debug SystemVerilog/UVM testbenches. \n \n Develop and execute Embedded C test programs for processor-based SoC verification. \n \n Execute regression tests, analyse failures and resolve simulation issues. \n \n Perform functional coverage analysis and drive coverage closure. \n \n Debug complex RTL simulation failures using waveform tools. \n \n Work with design teams to understand design changes and update verification environments. \n \n Support verification planning and sign-off activities. \n \n Required Technical Skills \n \n \n Strong hands-on experience with SystemVerilog and UVM . \n \n Experience in SoC or subsystem-level design verification. \n \n Good understanding of constrained-random verification, assertions, scoreboards and functional coverage. \n \n Experience modifying, enhancing and debugging existing UVM testbenches. \n \n Experience with Embedded C test development and debugging. \n \n Good understanding of SoC architecture, ARM processors, bus protocols and register interfaces. \n \n Strong RTL simulation debugging and waveform analysis skills. \n \n Experience in regression execution and coverage closure. \n \n Working knowledge of Python, Perl or Shell Scripting. \n \n Familiarity with version control systems and verification workflows. \n \n Candidate Requirements \n \n \n 5-20 years of relevant design verification experience. \n \n Strong debugging and problem-solving capabilities. \n \n Experience working with complex RTL designs and large SoC verification environments. \n \n Ability to independently manage verification activities. \n \n Experience adapting existing verification environments rather than only developing new testbenches. \n