Senior Verification Engineer in Hampshire

b Overview /b p In this role you will verify complex digital IP and modem subsystems for ASIC and FPGA implementations, ensuring functional and performance targets are met. You will build and maintain SystemVerilog/UVM environments, drive coverage and automation, and collaborate with RTL, architecture, and CI teams through tape-out. You’ll apply AI-assisted approaches to boost productivity while preserving quality and mentor junior engineers. The opportunity sits at the forefront of next-generation wireless and satellite communications, shaping high-performance digital design. /p b Responsibilities /b ul li Develop verification plans from architecture and design specs /li li Create and maintain SystemVerilog/UVM verification environments /li li Build testbenches, assertions, scoreboards, and coverage models /li li Perform directed and constrained-random verification /li li Drive coverage analysis and closure /li li Debug RTL and verification issues /li li Support IP/subsystem/system-level integration /li li Contribute to regression, automation, and CI workflows /li li Participate in design reviews and verification sign-off /li li Mentor junior engineers /li li Leverage AI-assisted methods to improve verification productivity while ensuring quality /li /ul b Key requirements /b ul li 3+ years of experience verifying digital ASIC and/or FPGA designs /li li Strong SystemVerilog and UVM experience /li li Good understanding of RTL design and digital hardware principles /li li Experience with coverage-driven and assertion-based verification /li li Strong debugging and problem-solving skills /li li Linux experience and scripting in Python, Tcl and/or Bash /li li Experience collaborating across RTL, architecture and verification teams /li li Degree in Electronic Engineering, Computer Engineering or a related discipline /li /ul ul li collaboration /li li mentoring /li li problem-solving /li li SystemVerilog /li li UVM /li li verification environments /li /ul