Overview
As part of a multidisciplinary engineering team, you will translate advanced communications algorithms into RTL implementations for ASIC and FPGA, enabling high-performance digital hardware for satellite-based connectivity. You will collaborate across Systems, Architecture, Verification and Physical Design to deliver integrated solutions throughout the lifecycle. You will optimize designs for timing, throughput, area and power, and produce clear technical documentation. This role offers hands-on work on world-first communications technology and the chance to influence next-generation hardware.
Responsibilities
- Translate system and algorithm requirements into efficient RTL micro-architectures
- Design and implement complex digital logic targeting both ASIC and FPGA platforms
- Develop simulation environments and testbenches to verify functionality
- Deploy designs onto FPGA development platforms for validation and system integration
- Optimise designs for timing, throughput, area and power efficiency
- Produce high-quality technical documentation, including design specifications and implementation documentation
- Work closely with Verification, Physical Design and Systems teams to deliver fully integrated solutions
- Contribute to engineering methodology, design flows and continuous process improvement
Key requirements
- Strong experience designing complex ASIC and/or FPGA digital systems
- Excellent RTL design skills using Verilog or SystemVerilog
- Experience optimising high-throughput digital designs for performance, timing and resource utilisation
- Knowledge of synthesis, timing analysis and power optimisation techniques
- Experience collaborating across multidisciplinary hardware development teams
- Comfortable producing clear technical documentation
- Strong experience using industry-standard simulation and synthesis tools
- collaboration across multidisciplinary teams
- ownership of RTL development
- clear technical documentation
- Verilog/SystemVerilog RTL design
- ASIC and/or FPGA digital design
- high-throughput design optimisation
Senior ASIC Design Engineer in Hampshire employer: Intellectual Capital Resources
Join a dynamic team where innovation meets collaboration, as we empower our Opto Mechanical Engineers to transform cutting-edge optical concepts into tangible products. Our supportive work culture fosters continuous learning and professional growth, with hands-on opportunities in a state-of-the-art laboratory environment. Located in a vibrant area, we offer competitive benefits and a chance to work alongside industry experts, making this an ideal place for those seeking meaningful and rewarding employment.
Contact Details:
Intellectual Capital Resources Recruitment Team
