This is a rare opportunity to apply your silicon design expertise to truly cutting-edge technology. Innovation sits at the core of this organisation, which develops foundational IP for market-leading graphics processors used in next-generation mobile, smart, and connected devices.
As a Digital ASIC Design Engineer, you will play a pivotal role in the design, debug, and optimisation of complex hardware modules, delivering best-in-class performance, power efficiency, and reliability.
You will join a highly skilled engineering team working at the forefront of GPU development. In this role, you will take ownership of sophisticated hardware designs, contribute to architectural decisions, and help drive technical excellence across projects.
What you’ll do
Collaborate with design, verification, and validation teams to deliver advanced silicon solutions
Define and document detailed micro-architecture specifications and execution plans aligned with project objectives
Analyse and optimise complex designs, balancing frequency, area, power, and performance trade-offs
Participate in design reviews, providing clear, constructive, and technically sound feedback
Maintain and improve the design environment, while tracking, debugging, and resolving design issues
Plan, schedule, and deliver assigned work packages to agreed timelines
Stay current with emerging tools, methodologies, and best practices in silicon design
Mentor graduate engineers and early-career colleagues, supporting their technical development and professional growth
Experience
What you will need to have
Strong knowledge of digital IC design techniques and methodologies
Hands-on experience with RTL design at IP or SoC level using SystemVerilog
Proven ability to optimise designs across performance, power, and area constraints
Experience with ASIC or FPGA design tools and environments
Exposure to formal verification or proof methodologies to capture and validate design intent
Knowledge of CPU, DSP, or FPU architectures, including debug and test strategies
Proficiency in C, SystemC, C++, Python, Perl, or TCL
Understanding of verification requirements derived from architectural and functional specifications
Experience with GPU or CPU design methodologies, including UVM
On offer is a competitive base salary and bonus scheme.
For more information on this role or others then please contact Jordan Browne at IC Resources.
Digital ASIC Design Engineer in Bristol employer: Intellectual Capital Resources
Join a dynamic team where innovation meets collaboration, as we empower our Opto Mechanical Engineers to transform cutting-edge optical concepts into tangible products. Our supportive work culture fosters continuous learning and professional growth, with hands-on opportunities in a state-of-the-art laboratory environment. Located in a vibrant area, we offer competitive benefits and a chance to work alongside industry experts, making this an ideal place for those seeking meaningful and rewarding employment.
Contact Details:
Intellectual Capital Resources Recruitment Team
