Hybrid Design Verification Engineer (SystemVerilog/UVM)

Hybrid Design Verification Engineer (SystemVerilog/UVM)

Full-Time On-site
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Intellectual Capital Resources Ltd. is seeking Design Verification Engineers to join a growing semiconductor group in Edinburgh.

You will contribute to digital verification for complete mixed-signal ICs, build advanced verification environments, and help improve methodologies across projects. This role offers a flat culture, strong development opportunities, and a competitive compensation package including RSUs.

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Hybrid Design Verification Engineer (SystemVerilog/UVM) employer: Intellectual Capital Resources Ltd

Intellectual Capital Resources Ltd is an exceptional employer located in the vibrant city of Glasgow, offering a dynamic work culture that fosters innovation and collaboration. Employees benefit from extensive growth opportunities in cutting-edge technology fields, particularly in embedded cryptography, while enjoying a supportive environment that values teamwork and professional development.

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Contact Details:

Intellectual Capital Resources Ltd Recruitment Team