We’re Hiring: Senior/Staff Verification Engineer in Bristol

As a Senior Staff Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.
Take full ownership of complex IP verification, developing System Verilog - UVM test bench environmentsCreate functional coverage models and write constrained random tests for thorough validationEnsure test benches meet sign-off targets, including coverage and functional safety requirementsDebug failing test cases and collaborate in Design and Concept meetings to resolve issuesDrive verification strategy and enhance IP test bench architecture for future projectsYour ProfileQualifications and skills to help you succeedWe are looking for a skilled verification engineer with a collaborative attitude and eagerness to apply and expand industry-standard methodologies.
Bachelor's degree in Electrical/Electronic Engineering or a related field8+ years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience)Strong understanding of verification concepts and System Verilog design and testbench fundamentalsEagerness to learn and apply industry-standard verification methodologies like UVMUnderstanding of debugging workflows and willingness to learn tools for test issue analysisStrong problem-solving skills, effective teamwork, and solid time managementFluency in EnglishPlease send us your CV in English.
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