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- Tasks: Lead the verification of complex ASIC designs using UVM and SystemVerilog.
- Company: Join a dynamic team focused on cutting-edge ASIC technology.
- Benefits: Enjoy a hybrid work model with competitive salary and additional perks.
- Why this job: Be part of a collaborative environment that values innovation and continuous learning.
- Qualifications: 10+ years in ASIC verification with expertise in SystemVerilog and UVM required.
- Other info: This is a 6-month contract with potential for permanent placement.
The predicted salary is between 56000 - 64000 £ per year.
Lead Verification Engineer
Bristol/Reading
I am seeking a dedicated and skilled ASIC Verification Engineer to join our dynamic team for a 6-month fixed contract with a view to go into a permanent position. The Lead Verification Engineer will have expertise in UVM and SystemVerilog to support the development and verification of complex ASIC designs.
Responsibilities
- Develop and implement verification environments using UVM methodology
- Create verification plans and test cases to ensure thorough testing of ASIC designs
- Collaborate with design and architecture teams to ensure comprehensive verification coverage
- Perform functional and code coverage analysis to validate the design
- Contribute to verification methodology improvements and best practices
Qualifications
- Bachelor's or Master's degree in Electrical Engineering or Computer Science
- 10+ years industry experience
- Proficiency in SystemVerilog and UVM for ASIC verification
- Solid understanding of digital design fundamentals
- Experience with industry-standard simulation and verification tools
- Strong problem-solving skills and attention to detail
- Excellent communication and teamwork abilities
Day-to-day
- Collaborate with the design and architecture teams to understand the ASIC specifications
- Develop and execute comprehensive verification plans to validate the functionality of the ASIC
- Troubleshoot and debug issues found during verification
- Contribute to the ongoing improvement of verification methodologies and processes
- Engage in regular team meetings and knowledge sharing sessions to foster continuous learning and improvement
This is a Hybrid role and you will be required to go onsite to either the company's Reading or Bristol office.
Salary £70,000 – £80,000 + other benefits
Start: As soon as possible
For more information, please contact Rachel Mason at IC Resources
Verification Lead employer: IC Resources
Contact Detail:
IC Resources Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Verification Lead
✨Tip Number 1
Make sure to highlight your experience with UVM and SystemVerilog in any discussions or interviews. These are crucial skills for the Lead Verification Engineer role, and demonstrating your expertise can set you apart from other candidates.
✨Tip Number 2
Prepare to discuss specific projects where you've developed verification environments or created verification plans. Being able to share concrete examples will showcase your hands-on experience and problem-solving abilities.
✨Tip Number 3
Familiarize yourself with the latest trends and best practices in ASIC verification methodologies. Showing that you are proactive about improving verification processes can demonstrate your commitment to excellence in this field.
✨Tip Number 4
Since this is a hybrid role, be ready to discuss your flexibility and willingness to work onsite in either Reading or Bristol. Emphasizing your adaptability can make you a more attractive candidate for the team.
We think you need these skills to ace Verification Lead
Some tips for your application 🫡
Understand the Role: Make sure to thoroughly read the job description for the Verification Lead position. Understand the key responsibilities and qualifications required, especially the emphasis on UVM and SystemVerilog expertise.
Tailor Your CV: Customize your CV to highlight your relevant experience in ASIC verification, particularly your proficiency in UVM and SystemVerilog. Include specific projects or achievements that demonstrate your skills and problem-solving abilities.
Craft a Strong Cover Letter: Write a cover letter that reflects your passion for the role and the company. Mention how your background aligns with the responsibilities listed, and provide examples of how you've contributed to verification methodologies in previous roles.
Highlight Team Collaboration: Since the role involves collaboration with design and architecture teams, emphasize your teamwork and communication skills in both your CV and cover letter. Provide examples of successful collaborations in past projects.
How to prepare for a job interview at IC Resources
✨Showcase Your Technical Expertise
Be prepared to discuss your experience with UVM and SystemVerilog in detail. Highlight specific projects where you developed verification environments and how you approached complex ASIC designs.
✨Demonstrate Problem-Solving Skills
Expect to face technical questions that assess your problem-solving abilities. Share examples of challenges you've encountered during verification and how you resolved them, emphasizing your attention to detail.
✨Emphasize Collaboration Experience
Since the role involves working closely with design and architecture teams, be ready to discuss your teamwork experiences. Provide examples of how you effectively communicated and collaborated to achieve project goals.
✨Prepare for Methodology Discussions
Familiarize yourself with current verification methodologies and be ready to discuss how you've contributed to improvements in past roles. This shows your commitment to best practices and continuous learning.
