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- Tasks: Lead the verification of complex ASIC designs using UVM and SystemVerilog.
- Company: Join a dynamic team focused on cutting-edge ASIC technology.
- Benefits: Enjoy a hybrid work model with competitive salary and additional perks.
- Why this job: Be part of a collaborative environment that values innovation and continuous learning.
- Qualifications: 10+ years in ASIC verification with expertise in SystemVerilog and UVM required.
- Other info: This is a 6-month contract with potential for permanent placement.
The predicted salary is between 56000 - 64000 £ per year.
We are seeking a highly skilled Verification Lead for an fixed term contract to join a dynamic team. If you have a passion for cutting-edge technologies, a proven ability to lead complex verification projects, and a desire to make a significant impact, this role is for you!
Key Responsibilities:
- Serve as a Subject Matter Expert (SME) within technical disciplines, providing guidance and decision-making expertise.
- Lead metric-driven verification , including planning, functional coverage, and code coverage.
- Design and implement SystemVerilog , UVM , ABV , unit-level and top-level verification , and testbench architecture .
- Independently contribute to technical projects, delivering results that exceed expectations.
- Proactively evaluate issues and define actionable solutions, applying advanced knowledge across technical functions.
- Contribute to the development of technical sales documents , including Statements of Work (SOW).
- Collaborate with the team to tackle complex challenges, solving problems efficiently and effectively.
Skills & Experience Required:
Essential:
- Expertise in SystemVerilog , UVM , ABV , constrained random verification .
- Hands-on experience in VHDL , PSL , SVA , and e .
- Solid understanding of RISC-V architecture, cache, and coherency concepts.
- Experience in formal verification , including model checking , CDC , coverage closure , and x-prop .
- Proficient in Power-aware verification using UPF or CPF , including RTL and gate-level simulation .
- SoC level verification expertise, including HW/SW co-verification and multi-mode simulation .
- Familiarity with HW acceleration , including emulation .
- Experience with verification infrastructure automation (e.g., Perl , Python , Java , Tcl , IP-XACT ).
Desirable:
- Advanced knowledge in RISC-V architectural concepts.
- Experience in multi-platform verification , from unit to top-level.
- In-depth knowledge of verification methodologies across various subsystems.
Key Attributes:
Essential:
- Strong leadership, communication , and negotiation skills .
- Proven ability to build trust through open and transparent communication.
- Reliable, self-motivated, and dedicated to delivering results.
- Excellent time management , problem-solving , and organizational skills.
- Ability to adapt to changing priorities and work efficiently under pressure.
- High attention to detail and a self-organized approach to tasks.
Why This Opportunity?
- Competitive rates for an interim contract position.
- Work with a forward-thinking team on industry-leading technology.
- Take ownership of important verification projects and make a real difference.
If you are ready to take on an exciting new challenge, apply today to join us as an Interim Verification Lead !
Verification Lead employer: Sondrel
Contact Detail:
Sondrel Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Verification Lead
✨Tip Number 1
Make sure to highlight your experience with UVM and SystemVerilog in any discussions or interviews. These are crucial skills for the Lead Verification Engineer role, and demonstrating your expertise can set you apart from other candidates.
✨Tip Number 2
Prepare to discuss specific projects where you've developed verification environments or created verification plans. Being able to share concrete examples will showcase your hands-on experience and problem-solving abilities.
✨Tip Number 3
Familiarize yourself with the latest trends and best practices in ASIC verification methodologies. Showing that you are proactive about improving verification processes can demonstrate your commitment to excellence in this field.
✨Tip Number 4
Since this is a hybrid role, be ready to discuss your flexibility and willingness to work onsite in either Reading or Bristol. Emphasizing your adaptability can make you a more attractive candidate for the team.
We think you need these skills to ace Verification Lead
Some tips for your application 🫡
Understand the Role: Make sure to thoroughly read the job description for the Verification Lead position. Understand the key responsibilities and qualifications required, especially the emphasis on UVM and SystemVerilog expertise.
Tailor Your CV: Customize your CV to highlight your relevant experience in ASIC verification, particularly your proficiency in UVM and SystemVerilog. Include specific projects or achievements that demonstrate your skills and problem-solving abilities.
Craft a Strong Cover Letter: Write a cover letter that reflects your passion for the role and the company. Mention how your background aligns with the responsibilities listed, and provide examples of how you've contributed to verification methodologies in previous roles.
Highlight Team Collaboration: Since the role involves collaboration with design and architecture teams, emphasize your teamwork and communication skills in both your CV and cover letter. Provide examples of successful collaborations in past projects.
How to prepare for a job interview at Sondrel
✨Showcase Your Technical Expertise
Be prepared to discuss your experience with UVM and SystemVerilog in detail. Highlight specific projects where you developed verification environments and how you approached complex ASIC designs.
✨Demonstrate Problem-Solving Skills
Expect to face technical questions that assess your problem-solving abilities. Share examples of challenges you've encountered during verification and how you resolved them, emphasizing your attention to detail.
✨Emphasize Collaboration Experience
Since the role involves working closely with design and architecture teams, be ready to discuss your teamwork experiences. Provide examples of how you effectively communicated and collaborated to achieve project goals.
✨Prepare for Methodology Discussions
Familiarize yourself with current verification methodologies and be ready to discuss how you've contributed to improvements in past roles. This shows your commitment to best practices and continuous learning.
