Test Engineer

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Business Manager – Semiconductor Division

UK – Bristol, Cambridge, or Thames Valley

£50,000 – £90,000 DOE + Share options and Bonus

5-10 years’ experience – Mid- Senior level

You must have prior experience at a Semiconductor company to be considered.

I am seeking a DFT Engineer to join a UK-headquartered fabless semiconductor company specializing in custom ASIC design and supply services. Known for working across a broad range of sectors — including automotive, industrial, healthcare, communications, and consumer electronics — the company provides both turnkey ASIC development and IP licensing, including processor subsystems and signal processing solutions.

You will have a strong academic record and 5-10 years’ experience in Design for Test (DFT) within digital ASIC/SoC development.

Responsibilities

• Take full-flow ownership of all DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs on an as-needed basis to meet customer project requirements.
• Setup, run, and maintain EDA tool flows relating to DFT, BIST, and test pattern generation.
• Work closely alongside the wider Front-end and Back-end teams to implement and verify DFT at all stages in the development flow.
• Take responsibility for setting and meeting customers fault-coverage expectations and requirements.
• Generate test specification documentation, as required, for delivery to sub-contractors providing test services.

Skillset

• 5-10 years’ experience in industry with a strong track record in DFT gained across several successful ASIC projects.
• Specific skills in DFT implementation:
• Specification at the architecture level
• Implementation using tool-based and hand-crafted methods
• Integration of IP including CPU’s, Analog Macros, and IO PHYs
• BIST and memory repair integration
• Coverage analysis and improvement to meet targets
• ATPG, as well as manual and semi-automatic TPG, including simulation-based methods.
• Implementation of at-speed test methodologies
• DFT for power-managed designs
• Generation of STA and scenario/mode constraints
• Good knowledge of a full EDA vendor DFT tool suite.
• Working knowledge of the complete SoC design flow and associated tools and methodologies to deliver working silicon.
• Experience of RTL and gate-level simulations and related debugging.

This role can be based in one of several UK locations and visa sponsorship can be provided.

For more information, please contact Rachel Mason at IC Resources.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing and Computer Hardware Manufacturing

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