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- Tasks: Ensure the correctness of complex ASIC designs using advanced verification methodologies.
- Company: Join a leading semiconductor powerhouse in Edinburgh's vibrant tech scene.
- Benefits: Competitive salary, RSUs, annual bonus, and a collaborative work environment.
- Why this job: Make a real impact in cutting-edge engineering while enjoying Edinburgh's quality of life.
- Qualifications: 5+ years in digital/mixed-signal verification with strong SystemVerilog skills.
- Other info: Mentor junior engineers and drive improvements in verification practices.
The predicted salary is between 48000 - 72000 £ per year.
Join a world-class semiconductor powerhouse in Edinburgh, one of Europe’s most attractive tech hubs. Known for its thriving semiconductor ecosystem, outstanding quality of life, and easy access to nature, Edinburgh offers the perfect balance between cutting-edge engineering work and lifestyle. This role provides an opportunity for experienced verification engineers to make a long-term move to the UK.
In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies.
Key Responsibilities- Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs
- Create and maintain UVM-based SystemVerilog testbenches
- Write, debug, and execute test cases to verify functionality, performance, and corner cases
- Perform block-level and full-chip verification, including simulation, coverage analysis, and regression management
- Collaborate closely with design engineers to interpret specifications and define verification requirements
- Analyse and resolve issues discovered during verification and post-silicon validation
- Mentor junior engineers and drive improvements in verification methodologies and infrastructure
- Participate in code reviews and contribute to continuous improvement of design and verification best practices
- 5+ years’ experience in digital and/or mixed-signal design verification
- Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
- Solid understanding of digital design principles, RTL design, and ASIC development flows
- Experience with scripting languages (Python, Perl, Shell, etc.)
- Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques
- Excellent problem-solving skills and attention to detail
- Competitive base salary plus RSUs and annual bonus
- A collaborative, innovative working environment
For more information on this role or others then please contact Jordan Browne for more information.
Senior Verification Engineer employer: IC Resources
Contact Detail:
IC Resources Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to your connections in the semiconductor industry, especially those in Edinburgh. A friendly chat can lead to insider info about job openings that might not even be advertised yet.
✨Tip Number 2
Show off your skills! Prepare a portfolio or a presentation that highlights your experience with UVM and SystemVerilog. When you get the chance to meet potential employers, having something tangible to share can really set you apart.
✨Tip Number 3
Practice makes perfect! Get ready for technical interviews by brushing up on your verification methodologies and problem-solving skills. Mock interviews with friends or colleagues can help you feel more confident when it’s time to shine.
✨Tip Number 4
Don’t forget to apply through our website! We’ve got loads of opportunities waiting for talented engineers like you. Plus, applying directly shows your enthusiasm and commitment to joining our team.
We think you need these skills to ace Senior Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Senior Verification Engineer role. Highlight your experience with SystemVerilog, UVM, and any relevant projects that showcase your skills in digital and mixed-signal design verification.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about this role and how your background aligns with our needs. Don’t forget to mention your problem-solving skills and attention to detail!
Showcase Your Technical Skills: In your application, be specific about your technical expertise. Mention the simulation tools you’ve used, your experience with scripting languages, and any methodologies you've implemented. We love seeing concrete examples!
Apply Through Our Website: We encourage you to apply through our website for a smoother process. It helps us keep track of your application and ensures you don’t miss out on any important updates from us!
How to prepare for a job interview at IC Resources
✨Know Your Verification Methodologies
Make sure you brush up on advanced verification methodologies, especially UVM and SystemVerilog. Be ready to discuss how you've applied these in your previous roles, as this will show your depth of knowledge and experience.
✨Prepare for Technical Questions
Expect technical questions that dive into digital and mixed-signal design verification. Review key concepts like RTL design and ASIC development flows, and be prepared to solve problems on the spot to demonstrate your problem-solving skills.
✨Showcase Your Collaboration Skills
Since collaboration with design engineers is crucial, think of examples where you've successfully worked in a team. Highlight how you interpreted specifications and defined verification requirements together, as this will showcase your teamwork abilities.
✨Mentorship Matters
If you've mentored junior engineers before, share those experiences! Discuss how you’ve driven improvements in verification methodologies and contributed to code reviews, as this will reflect your leadership potential and commitment to continuous improvement.
