Senior Staff RTL CPU Design Engineer - Equity & Relocation

Senior Staff RTL CPU Design Engineer - Equity & Relocation

Full-Time 70000 - 90000 Β£ / year (est.) No working from home possible
IC Resources

At a Glance

  • Tasks: Design cutting-edge CPU cores and collaborate with top engineers on exciting projects.
  • Company: Join a leading tech company shaping the future of processors.
  • Benefits: Relocation support, visa sponsorship, and competitive salary.
  • Other info: Opportunity for exceptional candidates to grow in a dynamic environment.
  • Why this job: Be at the forefront of technology and make a significant impact in CPU design.
  • Qualifications: 6+ years in RTL design with strong Verilog/SystemVerilog/VHDL skills required.

The predicted salary is between 70000 - 90000 Β£ per year.

IC Resources is seeking a Staff/Senior Staff RTL Design Engineer to help develop the next generation of world-class processors.

You will design CPU cores across the full design lifecycle, collaborating with top-tier architects and engineers on technically demanding projects.

The role requires 6+ years in RTL design with strong Verilog/System Verilog/VHDL skills, plus C/C++/Python programming and DSLs.

Relocation and visa sponsorship are available for exceptional candidates. #J-18808-Ljbffr

Senior Staff RTL CPU Design Engineer - Equity & Relocation employer: IC Resources

IC Resources is an exceptional employer, offering a dynamic work culture that fosters innovation and collaboration in the heart of Cirencester. With a strong commitment to employee growth, you will have access to continuous learning opportunities and the chance to work on cutting-edge projects that make a real impact in rugged hardware design. Join us to be part of a supportive team that values your expertise and encourages you to thrive in a challenging yet rewarding environment.

IC Resources

Contact Details:

IC Resources Recruitment Team

We think you need these skills to ace Senior Staff RTL CPU Design Engineer - Equity & Relocation

RTL Design
Verilog
SystemVerilog
VHDL
C++
Python
Domain-Specific Languages (DSLs)