At a Glance
- Tasks: Design and verify high-performance digital datapath logic for advanced ASIC products.
- Company: Join a global leader in innovative engineering based in Cambridge.
- Benefits: Competitive salary, bonuses, RSUs, and relocation support available.
- Other info: Opportunity for technical ownership and career growth in a dynamic environment.
- Why this job: Tackle challenging mathematical problems and lead exciting new design projects.
- Qualifications: Strong maths background and experience with Verilog/SystemVerilog required.
The predicted salary is between 60000 - 80000 £ per year.
I am seeking a Datapath Design Engineer to join a global company in their unique Engineering team based in Cambridge. This is a Principal/Staff level position and requires you to play a key role in the specification, design, and verification of high-performance digital datapath logic for advanced ASIC products and IP. This role requires strong mathematical ability, a solid understanding of digital design fundamentals, and hands-on expertise in Verilog and SystemVerilog.
To be considered you must have:
- Strong background in mathematics (e.g. numerical methods, linear algebra, signal processing, or similar)
- Proven experience designing RTL using Verilog and SystemVerilog
- Solid understanding of synchronous digital design, timing, and clock-domain considerations
- Experience designing arithmetic-heavy or algorithmic datapaths
- Floating-point or APU experience
- Ability to reason about precision, overflow, rounding, and numerical accuracy
- Familiarity with ASIC design flows from RTL through synthesis
- Any Verification skills would be highly advantageous
This role focuses on building new designs rather than maintaining legacy implementations, with opportunities to take technical ownership and lead projects. You will work on intellectually challenging, mathematics-driven problems and deliver new designs you can genuinely call your own.
As a top company you can expect a great benefits package which includes base, bonus and RSUs. Visa sponsorship can be given and relocation support can be provided if you are a technical match. This role is very specific, so please ensure you have relevant experience before applying.
Senior Datapath Design Engineer — RTL/Verilog, RSUs employer: IC Resources
Join a leading global company in Cambridge as a Senior Datapath Design Engineer, where you will be part of an innovative Engineering team dedicated to creating cutting-edge digital designs. With a strong emphasis on employee growth, the company offers a competitive benefits package including base salary, bonuses, and RSUs, alongside opportunities for technical ownership and project leadership in a collaborative work culture that values creativity and intellectual challenge. Relocation support and visa sponsorship are available, making this an attractive opportunity for talented engineers looking to make a significant impact in their field.
StudySmarter Expert Advice🤫
We think this is how you could land Senior Datapath Design Engineer — RTL/Verilog, RSUs
✨Tip Number 1
Network like a pro! Reach out to current employees in the company or industry on LinkedIn. A friendly chat can give you insider info and might even lead to a referral, which is always a bonus.
✨Tip Number 2
Prepare for those tricky technical interviews! Brush up on your Verilog and SystemVerilog skills, and be ready to discuss your past projects. We all know that hands-on experience speaks volumes, so showcase your best work.
✨Tip Number 3
Don’t underestimate the power of a good follow-up! After an interview, drop a quick thank-you email to express your appreciation. It keeps you fresh in their minds and shows your enthusiasm for the role.
✨Tip Number 4
Apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining our team at StudySmarter.
We think you need these skills to ace Senior Datapath Design Engineer — RTL/Verilog, RSUs
Some tips for your application 🫡
Tailor Your CV:Make sure your CV highlights your experience with RTL design using Verilog and SystemVerilog. We want to see how your skills match the specific requirements of the role, so don’t be shy about showcasing your mathematical prowess and any relevant projects you've worked on.
Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you’re passionate about building new designs and how your background in digital design fundamentals makes you a perfect fit for our Datapath team. Let us know what excites you about the role!
Showcase Your Problem-Solving Skills:In your application, highlight any experiences where you tackled complex mathematical problems or designed arithmetic-heavy datapaths. We love seeing how you approach challenges, so share specific examples that demonstrate your expertise and creativity.
Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it shows us you’re keen on joining our awesome team at StudySmarter!
How to prepare for a job interview at IC Resources
✨Know Your Maths
Brush up on your mathematical concepts, especially numerical methods and linear algebra. Be ready to discuss how these principles apply to your previous projects, particularly in relation to designing arithmetic-heavy datapaths.
✨Showcase Your RTL Skills
Prepare to talk about your experience with Verilog and SystemVerilog. Have specific examples ready that demonstrate your ability to design and verify high-performance digital logic, as this will be crucial for the role.
✨Understand Digital Design Fundamentals
Make sure you can explain synchronous digital design, timing, and clock-domain considerations clearly. The interviewers will want to see that you have a solid grasp of these concepts and can apply them effectively.
✨Be Ready for Technical Ownership
Since this role involves building new designs, think about instances where you've taken ownership of a project. Be prepared to discuss how you led the design process and tackled any challenges that arose.
