Design Verification Engineer
Design Verification Engineer

Design Verification Engineer

Cambridge Full-Time 36000 - 60000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Own functional verification for cutting-edge hardware systems in quantum computing.
  • Company: Join a rapidly growing HW Team in Cambridge, working on innovative technology.
  • Benefits: Enjoy learning opportunities, collaboration with experts, and potential visa sponsorship.
  • Why this job: Be part of a cross-disciplinary team and contribute to high-performance solutions.
  • Qualifications: Strong experience in functional verification and testbench design; familiarity with programming languages required.
  • Other info: Work onsite 3 days a week in Cambridge; no prior quantum experience needed.

The predicted salary is between 36000 - 60000 £ per year.

Job Description

A US-based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team, this company offers a unique opportunity to be part of the AI revolution from the ground up.

As AI and computing rapidly evolve, there is an increasing demand for sophisticated platforms that integrate a wide range of processors—including CPUs, GPUs, and neural accelerators and this is where you come in!

You will be joining a Fabric IP company as a Design Verification Engineer, contributing your strong background in developing testbenches and writing test sequences for complex IPs. In this role, you will play a pivotal part in shaping the company’s technology portfolio—bringing both technical expertise and creative problem-solving to innovative hardware solutions.

Responsibilities:

  • Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
  • Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
  • Collaborate with software teams to define and implement configurable testbenches
  • Work with design teams test plans, failure debug, coverage, etc.

Qualifications and Preferred Skills

  • BS, MS in Electrical Engineering, Computer Engineering or Computer Science
  • 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification
  • Proficiency in Verilog, SystemVerilog
  • Familiarity with industry-standard EDA tools for simulation and debug
  • Deep experience with UVM-based testbenches
  • Experience with modern programming languages like Python
  • Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
  • Understanding of Arm CHI protocol is a plus
  • Experience on working with IP's for caches, cache coherency, memory subsystems, interconnects, and NoC's is a plus
  • Experience with formal verification techniques, emulation platforms is a plus
  • Excellent problem-solving skills and attention to detail
  • Strong communication and collaboration skills

On offer is a competitive base salary of up to £120,000 (dependent on experience), along with share options and a performance-based bonus scheme

This is a rare opportunity to join the company as one of the first engineers in the UK—and among a select few globally—helping to shape and build a world-class hardware team from the ground up

To be considered for this role, you must already be living and working in the United Kingdom and happy to work onsite in either Bristol or Cambridge.

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Contact Detail:

IC Resources Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Design Verification Engineer

✨Tip Number 1

Familiarise yourself with the latest trends in quantum computing and hardware verification. This will not only help you understand the context of the role better but also allow you to engage in meaningful conversations during interviews.

✨Tip Number 2

Network with professionals in the field by attending relevant meetups or online webinars. Building connections can provide insights into the company culture and may even lead to referrals, which can significantly boost your chances of landing the job.

✨Tip Number 3

Brush up on your SystemVerilog and UVM skills through practical projects or online courses. Being able to demonstrate your proficiency in these areas during discussions can set you apart from other candidates.

✨Tip Number 4

Prepare thoughtful questions about the company's verification processes and team dynamics. Showing genuine interest in how they operate can leave a positive impression and highlight your enthusiasm for the role.

We think you need these skills to ace Design Verification Engineer

Functional Verification
Verification Strategy Development
Testbench Design using UVM or OVM
SystemVerilog Proficiency
SystemVerilog Assertions (SVA)
Programming Skills in C, C++, and Python
Regression Tracking
Bug Tracking
Coverage Metrics Analysis
Collaboration with Hardware Designers
Cross-Disciplinary Teamwork
Self-Checking Test Design
Directed and Randomised Testing

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience in functional verification and any relevant projects. Emphasise your expertise in SystemVerilog, UVM or OVM frameworks, and any programming languages you are proficient in.

Craft a Compelling Cover Letter: Write a cover letter that showcases your passion for technology and your eagerness to learn about quantum computing. Mention how your skills align with the role and express your enthusiasm for working in a cross-disciplinary environment.

Highlight Relevant Experience: In your application, focus on specific examples of your previous work in verification strategy and planning. Discuss any challenges you faced and how you overcame them, particularly in relation to testbench design and maintaining verification environments.

Proofread Your Application: Before submitting, carefully proofread your application for any spelling or grammatical errors. A polished application reflects your attention to detail, which is crucial for a role in verification engineering.

How to prepare for a job interview at IC Resources

✨Understand the Role

Make sure you thoroughly understand the responsibilities of a Senior Verification Engineer. Familiarise yourself with functional verification, SystemVerilog, and the specific technologies mentioned in the job description, such as UVM or OVM.

✨Showcase Your Experience

Prepare to discuss your previous experience in functional verification. Be ready to provide examples of how you've defined verification strategies and implemented test environments in past roles.

✨Demonstrate Problem-Solving Skills

Expect technical questions that assess your problem-solving abilities. Think about how you would approach common challenges in verification and be prepared to explain your thought process clearly.

✨Ask Insightful Questions

Prepare thoughtful questions about the team, projects, and company culture. This shows your genuine interest in the role and helps you determine if it's the right fit for you.

Design Verification Engineer
IC Resources
Location: Cambridge

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