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- Tasks: Join a dynamic team to verify cutting-edge mixed signal IC developments.
- Company: Global organisation based in Edinburgh with a flat culture.
- Benefits: Hybrid work, personal development, and a supportive team environment.
- Why this job: Get hands-on with innovative projects and improve verification methodologies.
- Qualifications: Degree in Electronics/Computer Science and experience in digital verification.
- Other info: Exciting career growth opportunities in a collaborative setting.
The predicted salary is between 36000 - 60000 £ per year.
Join a world-class semiconductor powerhouse and play a key role in cutting-edge ASIC development.
I am looking for a Senior Design Verification Engineer to join a dynamic hardware development team in Edinburgh. In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies.
Key responsibilities
- Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs
- Create and maintain UVM-based SystemVerilog testbenches.
- Write, debug, and execute test cases to verify functionality, performance, and corner cases
- Perform block-level and full-chip verification, including simulation, coverage analysis, and regression management
- Collaborate closely with design engineers to interpret specifications and define verification requirements
- Analyse and resolve issues discovered during verification and post-silicon validation
- Mentor junior engineers and drive improvements in verification methodologies and infrastructure
- Participate in code reviews and contribute to continuous improvement of design and verification best practices
Qualifications
- 5+ years’ experience in digital and/or mixed-signal design verification
- Strong proficiency inSystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
- Solid understanding of digital design principles, RTL design, and ASIC development flows
- Experience with scripting languages (Python, Perl, Shell, etc.)
- Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques
- Excellent problem-solving skills and attention to detail
What’s on offer
- Competitive base salary plus RSUs and annual bonus
- A collaborative, innovative working environment
- Flexible work options – remote work may be considered for UK-based engineers with full right to work in the UK
Design Verification Engineer employer: IC Resources
Contact Detail:
IC Resources Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Design Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to current or former employees at the company you're eyeing. A friendly chat can give you insider info and maybe even a referral, which can really boost your chances.
✨Tip Number 2
Prepare for the interview by brushing up on your technical skills. Make sure you can talk confidently about your experience with SystemVerilog, UVM/OVM, and any relevant projects you've worked on. We want to see that passion shine through!
✨Tip Number 3
Showcase your problem-solving skills during interviews. Be ready to discuss how you've tackled complex verification challenges in the past. We love hearing about your hands-on experience and how you’ve improved methodologies.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining our team.
We think you need these skills to ace Design Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Design Verification Engineer role. Highlight your relevant experience and skills, especially in areas like SystemVerilog and testbench design. We want to see how you can contribute to our team!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about verification engineering and how your background aligns with our needs. Keep it engaging and personal – we love getting to know our applicants!
Showcase Your Projects: If you've worked on any relevant projects, make sure to mention them! Whether it's a complex IC development or a unique verification methodology, we want to see what you've accomplished. It helps us understand your hands-on experience.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy – just follow the prompts and submit your materials!
How to prepare for a job interview at IC Resources
✨Know Your Verification Methodologies
Make sure you brush up on your knowledge of verification methodologies like UVM and OVM. Be ready to discuss how you've applied these in past projects, as well as any improvements you've made to existing processes.
✨Showcase Your Technical Skills
Prepare to demonstrate your technical expertise in SystemVerilog and debugging skills. Bring examples of your work, such as testbenches you've designed or complex ICs you've verified, to illustrate your capabilities.
✨Understand the Role's Requirements
Familiarise yourself with the specific responsibilities listed in the job description. Be prepared to explain how your experience aligns with leading teams, creating test plans, and contributing to verification discussions.
✨Ask Insightful Questions
Prepare thoughtful questions about the company's verification practices and team dynamics. This shows your genuine interest in the role and helps you assess if the company culture is a good fit for you.
