IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own custom analog layout and verification of circuits, cells, blocks, and IP for high-speed SerDes and memory IO in advanced semiconductor technology nodes. Hybrid working is available with 3 days a week in the office.
The ideal candidate will have a strong background in analog IC layout, particularly on high-speed designs, with proficiency in Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, and parasitics extraction.
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Senior IC Layout Engineer — Hybrid, High-Speed SerDes in Cambridge employer: IC Resources
Join a forward-thinking semiconductor company that values innovation and excellence in digital design. With a strong emphasis on mentorship and professional growth, you'll thrive in a collaborative environment where your leadership will directly impact the success of complex ASIC/FPGA projects. Located in a vibrant tech hub, this role offers unique opportunities to shape methodologies and drive cutting-edge solutions while enjoying a supportive work culture that prioritises employee development.
