Design Verification Engineer in Preston

Design Verification Engineer in Preston

Preston Full-Time 50000 - 65000 € / year (est.) No home office possible
iBSC

At a Glance

  • Tasks: Verify cutting-edge designs and develop new test cases for complex protocols.
  • Company: Leading tech firm focused on high-performance computing solutions.
  • Benefits: Attractive salary, flexible working hours, and opportunities for skill enhancement.
  • Other info: Collaborative culture with strong potential for career advancement.
  • Why this job: Join a dynamic team and contribute to groundbreaking technology in a fast-paced environment.
  • Qualifications: Experience with UVM/SV and complex HPC protocols like PCIe and DDR.

The predicted salary is between 50000 - 65000 € per year.

My client has an urgent request for a number of design verification.

Prerequisites:

  • This is for individual contributor (IC) role.
  • Solid background on UVM/SV.
  • Experience in any of the complex HPC protocols (PCIe/DDR/LPDDR/Ethernet).
  • Knowledge on the usage of protocol VIPs.
  • Ability to define and write new test cases from scratch.
  • Working as part of a team but with autonomous debug capability.

Job Description:

  • For PCIe Controller verification, DDR/LPDDR Controller verification, UAL Controller verification and AMBA Peripheral Verification.
  • Looking for solid background on UVM/SV.
  • Protocols: PCIe (gen7 etc), CXL, High Speed Ethernet, DDR/LPDDR.
  • Experience in complex HPC protocols, using protocol VIPs.
  • Ability to define and write new test cases, working as part of a team but with autonomous debug capability.

Tools: Synopsys simulators/flow.

Design Verification Engineer in Preston employer: iBSC

As a Design Verification Engineer at our company, you will thrive in a dynamic and innovative environment that prioritises employee growth and collaboration. We offer competitive benefits, a supportive work culture that encourages autonomy and creativity, and opportunities to work on cutting-edge technologies in a prime location. Join us to be part of a team that values your expertise and fosters your professional development.

iBSC

Contact Detail:

iBSC Recruiting Team

StudySmarter Expert Advice🤫

We think this is how you could land Design Verification Engineer in Preston

Tip Number 1

Network like a pro! Reach out to your connections in the design verification field and let them know you're on the lookout for opportunities. You never know who might have the inside scoop on a role that fits your skills perfectly.

Tip Number 2

Show off your skills! Create a portfolio showcasing your experience with UVM/SV and complex HPC protocols. This can be a game-changer during interviews, as it gives potential employers a tangible look at what you can bring to the table.

Tip Number 3

Practice makes perfect! Prepare for technical interviews by brushing up on your knowledge of PCIe, DDR/LPDDR, and other relevant protocols. Mock interviews with friends or colleagues can help you feel more confident when it’s time to shine.

Tip Number 4

Don’t forget to apply through our website! We’ve got loads of opportunities waiting for talented individuals like you. Plus, applying directly can sometimes give you an edge over other candidates.

We think you need these skills to ace Design Verification Engineer in Preston

UVM
SystemVerilog (SV)
PCIe
DDR
LPDDR
CXL
High Speed Ethernet

Some tips for your application 🫡

Tailor Your CV:Make sure your CV highlights your solid background in UVM/SV and experience with complex HPC protocols like PCIe and DDR. We want to see how your skills match the role, so don’t be shy about showcasing relevant projects!

Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you’re the perfect fit for the Design Verification Engineer role. Mention your ability to define and write new test cases and your autonomous debug capability – we love that!

Showcase Teamwork and Autonomy:In your application, highlight examples where you’ve worked as part of a team but also taken the lead on debugging tasks. We value both collaboration and independence, so let us know how you balance the two!

Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy – just a few clicks and you’re done!

How to prepare for a job interview at iBSC

Know Your Protocols Inside Out

Make sure you brush up on your knowledge of complex HPC protocols like PCIe, DDR, and Ethernet. Be ready to discuss specific projects where you've used these protocols, as well as any challenges you faced and how you overcame them.

Show Off Your UVM/SV Skills

Since a solid background in UVM and SystemVerilog is crucial, prepare to demonstrate your expertise. Think of examples where you've defined and written new test cases from scratch, and be ready to explain your thought process during the verification process.

Team Player with a Twist

While teamwork is key, they’ll want to see your autonomous debugging skills too. Prepare to share instances where you’ve worked collaboratively but also taken the lead on debugging issues independently. Highlight your ability to balance both roles.

Familiarise Yourself with Tools

Get comfortable with Synopsys simulators and flows, as these are likely to come up in conversation. If you have experience with specific tools, be prepared to discuss how you’ve used them effectively in past projects.