Senior Principal CPU Architect in Cambridge

We are seeking a visionary and technically accomplished Senior Principal CPU Architect based in Cambridge, England, to lead the definition, modeling, and co‑design of next‑generation high‑performance CPU architectures. In this highly strategic role, you will bridge the gap between evolving software paradigms and silicon implementation, charting the course for industry‑leading compute engines.

Key Responsibilities

• Long‑Range Architecture Roadmap (N+1 & N+2): Drive the pathfinding and definition phases for microarchitectural features 3 to 5 years ahead of production, including fetch/decode stages, execution pipelines, out‑of‑order schedulers, and multi‑level memory hierarchies.
• ISA Definition & Evolution: Evaluate, propose, and formally specify new Instruction Set Architecture capabilities (e.g., matrix vector extensions, custom compute instructions, dynamic scheduling helpers) to optimize future compute frameworks.
• Emerging Workload & Performance Analysis: Profile, dissect, and project performance characteristics of next‑generation workloads and translate complex algorithmic bottlenecks into foundational microarchitectural requirements.
• Hardware/Software Co‑Design: Partner tightly with compiler teams, operating systems engineers, and application software architects to build end‑to‑end hardware acceleration capabilities, optimizing compilers alongside custom execution blocks.
• Cycle‑Accurate Modeling & Exploration: Oversee and guide the creation of C++/Python‑based cycle‑accurate simulation models to validate architectural concepts, trade‑offs, performance speedups, and area/power efficiency (PPA).
• Technical Leadership & Ecosystem Influence: Act as an elite technical individual contributor, influencing senior executive roadmaps and championing technical standards in international microarchitecture and ISA working committees.

Required Qualifications

• Deep Architecture Expertise: Proven track record in high‑performance CPU core development (e.g., x86, ARM, or RISC‑V) with deep knowledge of Out‑of‑Order execution, branch prediction, renaming, speculative execution, cache hierarchies, and coherency protocols.
• ISA Mastery: Authoritative understanding of ISA‑level designs, exception models, memory consistency models, and virtualization extensions.
• Workload Profiling: Proficiency using hardware performance counters, simulation traces (SimPoints, execution traces), and profiling tools (VTune, Perf) on large‑scale cloud, edge, or client workloads.
• Advanced Modeling Skills: Strong hands‑on experience developing cycle‑accurate architectural simulators (such as gem5 or proprietary internal simulators) using C, C++, and Python.
• Education & Experience: MS/PhD in Computer Engineering, Computer Science, or Electrical Engineering with a minimum of 12+ years of industry experience in CPU architecture and pathfinding.

Desired Qualifications

• Experience delivering multiple taped‑out high‑performance CPU silicon designs.
• Active contributions to open‑source architectural frameworks, compiler backends (LLVM/GCC), or open ISA working groups (e.g., RISC‑V International).
• Familiarity with advanced silicon packaging (chiplets, 3D stacking) and their microarchitectural implications.