Senior Digital Design Engineer in London

Mon-Fri, 37.5 hours per week. 50% hybrid

Mint Neuro is an innovative startup at the intersection of neurotechnology and semiconductors.

We are pioneering integrated circuit solutions for implantable medical devices targeting the management and treatment of neurological conditions.

Role

As a Senior Digital Design Engineer at Mint Neuro, you will lead and take ownership of the front-end digital design and verification for our next-generation mixed-signal ASICs ("Big A, Little D").

In our implantable neural interfaces, the digital subsystem plays a vital role in orchestrating, controlling, and monitoring ultra-low-power analog frontends, stimulation engines, and telemetry.

We are seeking an engineer who excels at writing clean, synthesizable Verilog/System Verilog and developing robust verification environments.

You will play a key hands-on role in taking digital architectures from concept and specification through RTL implementation, front-end verification, synthesis handoff, and lab bring-up in a collaborative, fast-paced R&D team.

Duties and Responsibilities

• A. Digital Architecture and RTL Development
• Lead the architecture, specification, and implementation of digital control, telemetry/serial communication, and power sequencing for mixed-signal ASICs.
• Develop clean, maintainable, and synthesizable Verilog/System Verilog RTL with a strong focus on safe, ultra low-power operation.
• Collaborate closely with analog IC designers to define mixed-signal boundaries, control register maps, clock generation, and analog calibration/trim routines.
• B. Verification, Safety and Quality Assurance
• Define verification strategies and build self-checking testbenches (System Verilog) at block and system level to ensure thorough functional coverage.
• Implement functional safety and fault-tolerant mechanisms (e. g. state machine protection, parity/CRC, watchdogs, reset monitoring) for safety-critical product reliability.
• Perform front-end RTL quality checks including linting, clock/reset-domain crossing (CDC/RDC) analysis, and static timing review.
• Support product risk-management activities (hazard analysis, FMEA/FMEDA) and participate in design reviews for high-reliability systems.
• C. Silicon Bring-up and Backend Collaboration
• Collaborate with the multidisciplinary team during silicon bring-up, bench testing, and validation across digital and analog interfaces.
• Support front-end synthesis, timing constraints (SDC), and STA closure-utilising in-house backend tools/scripts and/or coordinating with external backend partners.
• Support pre-silicon validation and hardware emulation using FPGAs where beneficial.
• D. Documentation and Team Collaboration
• Produce clear architecture specifications, register map documentation, verification plans, and technical review records.
• Work closely with the wider engineering team spanning analog design, system hardware, and software/firmware integration.

Qualifications

• A degree, or equivalent practical experience, in Electrical/Electronic Engineering, Computer Engineering, or a related discipline.
• Strong track record in front-end digital ASIC design and synthesis using Verilog or System Verilog.
• Demonstrated experience in digital verification, including developing structured, self-checking testbenches, assertions, and coverage analysis.
• Familiarity with front-end design quality flows: linting, clock-domain crossing (CDC) analysis, and timing constraints/STA.
• Ability to take technical ownership of the digital subsystem and drive designs through to tape-out.
• Strong collaborative and communication skills, with the motivation to thrive in an agile, fast-paced startup environment.
• Greatly Beneficial
• Safety-Critical

Design: Experience designing for safety-critical systems or high-reliability applications-especially under standards such as ISO 26262 (automotive), IEC 61508 (industrial), or medical device standards (ISO 13485 / IEC 60601 / IEC 62304).

• Mixed-Signal Integration: Practical experience with mixed-signal interfaces, register banking, and analog control/calibration logic.
• Bonus / Nice-to-Have
• Backend

Experience: Familiarity with backend ASIC flows (physical synthesis, STA, DFT/scan insertion, or place-and-route)-either hands-on or working with outsourced backend partners.

• FPGA Prototyping: Experience prototyping designs on FPGAs for emulation and early validation.
• Memory IP blocks: Experience working with SRAM, fuse and OTP memory IPs.

What We Offer

• Work Environment: Dynamic, innovative, and inclusive workplace culture.
• Location Perks: Modern offices and labs located in the heart of London.
• Flexible Working: Hybrid model, allowing up to 50% remote work.
• Compensation: Competitive salary with a comprehensive benefits package.
• Career Development: Work closely with experienced leadership in a high-growth startup with clear development paths.
• Purpose: Be part of a mission-driven team dedicated to making a positive impact on millions of lives worldwide.
• Private Healthcare, Dental and Optical cover.
• 33 days annual leave (including bank holidays).
• Socials, team building and Company days.

We recognise that expertise comes in many forms and that passion drives progress. Even if your experience doesn't perfectly align with every qualification in this job description, we encourage you to apply. We value a diverse range of perspectives and foster an inclusive environment, which opens doors for individuals committed

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