Field-Programmable Gate Arrays Engineer in Slough

I\’m getting in touch because I\’m supporting a client who are pushing the boundaries of high-performance IP on next generation FPGA and Adaptive SoC platforms and your experience looks highly relevant.

They require someone with strong SystemVerilog RTL capability, confident across 100Gb Ethernet, PCIe Gen5 and AXI, and comfortable taking designs through to timing closure without fuss. Vivado and Vitis are central to the toolflow, and there\’s real value placed on engineers who streamline their work with Python or Tcl. Modern development practices are in place, Git and CI included.

The role is fully remote from the UK with genuine technical ownership and a culture that respects engineering excellence. If this aligns even just slightly with what you\’d consider for your next move, would you be open to a brief conversation?