A leading tech consultancy is seeking a Mid-Senior level engineer with strong SystemVerilog RTL capabilities for a fully remote role from the UK. You will possess confidence across 100Gb Ethernet, PCIe Gen5, and AXI while being comfortable taking designs through to timing closure. Experience with Vivado and Vitis, and proficiency in Python or TCL to streamline work is essential. Join a culture that respects engineering excellence and offers genuine technical ownership.
#J-18808-Ljbffr
Remote FPGA Engineer – SystemVerilog & PCIe Gen5 in England employer: Gazelle Global
At Gazelle Global, we pride ourselves on being an exceptional employer that fosters a collaborative and innovative work culture. Our team members benefit from extensive professional development opportunities, competitive compensation, and the chance to lead transformative projects in a dynamic environment. Located in a vibrant area, we offer a unique blend of work-life balance and career growth, making us an ideal choice for those seeking meaningful and rewarding employment.
