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- Tasks: Develop cutting-edge FPGA systems and collaborate on innovative engineering projects.
- Company: Join a leading investment platform with a focus on low-latency technology.
- Benefits: Competitive pay, annual bonus, free lunch, and 35 days of leave.
- Why this job: Make a real impact in a dynamic team while enjoying a great work/life balance.
- Qualifications: Experience in HDL development and collaborative engineering skills.
- Other info: Enjoy monthly events and a relaxed dress code in a supportive environment.
The predicted salary is between 36000 - 60000 £ per year.
The Low Latency Engineering Group is responsible for a low-latency system that forms a critical part of our clients’ global investment platform. The group includes teams responsible for market-data, order-entry and order-execution functions. This team has deployed a bespoke, cutting-edge FPGA-based platform that enables our clients to exploit low-latency opportunities in the most competitive markets in the world. The team is now expanding to accelerate the deployment of this platform more widely.
The LLE FPGA team is a small team of software and hardware engineers. It’s responsible for its own QA, tooling and continuous delivery pipelines. We value flexibility and willingness to collaborate on the problems we work on alongside our clients.
Key responsibilities of the role include:
- Developing RTL HDL in SystemVerilog
- Writing automated test benches
- Writing scripts in Python
- Developing software in C/C++
- Building Continuous Delivery pipelines for all components
Who are we looking for?
You will be an enthusiastic and capable Engineer who is able to solve real-world problems in HDL and software. You should be flexible and proactive, with the ability to make complex systems work and to debug them when they don’t. You should enjoy working as part of a collaborative engineering team.
The ideal candidate will have the following skills and experience:
- Practical experience of hardware/software co-design for FPGA-based systems
- HDL development skills in SystemVerilog
- Experience with Xilinx FPGA Build Process
- System analysis and debugging skills
- Ability to communicate well with technical and non-technical people
- Experience working in a collaborative engineering team, preferably using a git-based development workflow
The following skills and experiences are beneficial, but not essential:
- C or C++ knowledge
- Python knowledge
Why should you apply?
- Highly competitive compensation plus annual discretionary bonus
- Lunch provided (via Just Eat for Business) and dedicated barista bar
- 35 days’ annual leave
- 9% company pension contributions
- Informal dress code and excellent work/life balance
- Comprehensive healthcare and life assurance
- Cycle-to-work scheme
- Monthly company events
FPGA Engineer in London employer: G-Research
Contact Detail:
G-Research Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land FPGA Engineer in London
✨Tip Number 1
Network like a pro! Reach out to current employees in the FPGA field on LinkedIn or at industry events. A friendly chat can give you insider info and maybe even a referral!
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your HDL projects, scripts, and any FPGA work you've done. This will help you stand out and demonstrate your hands-on experience.
✨Tip Number 3
Prepare for technical interviews by brushing up on SystemVerilog and C/C++. Practice coding challenges and be ready to discuss your problem-solving approach with real-world examples.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets noticed. Plus, we love seeing candidates who are proactive about their job search!
We think you need these skills to ace FPGA Engineer in London
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with HDL development and FPGA systems. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects or achievements!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re excited about the role and how your background makes you a great fit for our team. We love seeing enthusiasm and a bit of personality!
Showcase Your Collaboration Skills: Since we value teamwork, mention any experiences where you’ve worked in collaborative environments. Whether it’s through git-based workflows or joint problem-solving, let us know how you thrive in a team setting.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way to ensure your application gets into the right hands. Plus, it shows us you’re keen on joining our awesome team!
How to prepare for a job interview at G-Research
✨Know Your HDL Inside Out
Make sure you brush up on your SystemVerilog skills before the interview. Be prepared to discuss your past projects involving HDL development and how you've tackled challenges in that area. Having specific examples ready will show your expertise and enthusiasm for the role.
✨Show Off Your Debugging Skills
Since the role involves system analysis and debugging, be ready to talk about your approach to troubleshooting complex systems. Share a story where you successfully identified and resolved an issue, highlighting your problem-solving skills and technical knowledge.
✨Collaborate Like a Pro
This team values collaboration, so be prepared to discuss your experience working in a team environment. Talk about how you've used git in past projects and how you communicate with both technical and non-technical team members. This will demonstrate your ability to fit into their collaborative culture.
✨Get Familiar with Continuous Delivery
Since building Continuous Delivery pipelines is part of the job, it’s a good idea to understand the basics of CI/CD processes. If you have experience with any tools or frameworks related to this, mention them during the interview. Showing that you’re proactive about learning and adapting will impress the interviewers.
