A Global semiconductor giant based in Cambridge are seeking to bolster their team with a talented Formal Verification Engineer.
Please note this opportunity is based on-site in Cambridge.
Responsibilities:
- Develop a deep understanding of the 3D graphics hardware pipeline, including feature sets, data paths, block functionalities, and interfaces
- Plan and implement Formal Property Verification (FPV) strategies, including assertion-based testbenches, formal proofs, and sign-off matrices
- Collaborate with GPU architecture, RTL design, and DV teams globally to ensure project goals and quality targets are met
- Debug RTL artifacts, drive coverage closure, and resolve complex verification challenges in formal proof environments
- Engage with EDA vendors and explore innovative formal verification methodologies to enhance verification quality and efficiency
Requirements:
- Hands-on experience with industry-standard formal verification tools and techniques
- Proficiency in writing SystemVerilog Assertions and managing formal proof complexity using abstraction methods
- Strong experience in bug-hunting, coverage closure, and achieving formal verification sign-off
- Knowledge of GPU architecture is advantageous but not required; familiarity with additional formal applications such as DPV, C-to-RTL SEQ, or RTL-to-RTL SEQ is a plus
- Excellent communication skills, ability to learn quickly, and a proactive approach to delivering high-quality results
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)
#J-18808-Ljbffr
Contact Detail:
European Tech Recruit Recruiting Team