Senior CPU Hardware Performance Architect - CPU Simulations / Microarchitecture / C++ / Python in Cambridge

Senior CPU Hardware Performance Architect - CPU Simulations / Microarchitecture / C++ / Python

Join a global technology organisation researching and developing next-generation high-performance computing architectures and microarchitectural innovations. Operating at the forefront of semiconductor innovation, silicon design, and workload acceleration, the company is building foundational CPU cores designed to power compute-intensive workloads across future processing platforms.

This senior-level performance architecture role offers the opportunity to drive microarchitectural exploration and quantitative performance modeling for future high-performance processors. The position combines cycle-accurate simulation, workload profiling, bottleneck analysis, microarchitectural innovation, and performance-power-area optimization.

This is an on-site position based in Cambridge, UK.

Role Overview

You will take technical ownership of CPU performance modeling, workload characterization, and quantitative trade-off analysis on-site in Cambridge.

Your responsibilities will span the entire performance engineering lifecycle—from constructing C++/Python-based simulation models and profiling complex software workloads to identifying hardware execution bottlenecks, proposing novel pipeline features, and evaluating performance, power, and area (PPA) impacts to guide silicon design decisions.

Key Responsibilities

• Collaborate with hardware and software engineering teams to define microarchitectural specifications for next-generation CPU cores.
• Develop, refine, and maintain high-fidelity, cycle-accurate and functional C++/Python simulators to evaluate emerging pipeline concepts.
• Propose innovative microarchitecture features across core execution structures and rigorously quantify their impact on overall processing throughput.
• Profile complex software workloads, isolate microarchitectural bottlenecks, and conduct sensitivity analysis to guide core optimization.
• Partner with compiler, OS, and hardware design groups to translate workload insights into actionable hardware specifications.
• Execute pre-silicon performance validation and trade-off studies balancing throughput gains against power and die area budgets.

Required Experience

• Strong background in CPU microarchitecture, with deep technical understanding of core execution structures (such as fetch/decode, branch prediction, out-of-order dispatch, load/store units, prefetchers, and memory hierarchies).
• Master’s or Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field (or PhD).
• Practical experience in performance profiling, workload characterization, and low-level software analysis.
• Strong software engineering skills with modern C++ and Python for simulation and modeling toolchain development.
• Demonstrated understanding of performance, power, and area (PPA) trade-offs in high-performance CPU design.
• Preferred: Hands-on experience with cycle-accurate CPU simulators, pre-silicon performance analysis, or microarchitectural pathfinding.
• Preferred: Track record of taking microarchitectural concepts from early exploration toward production silicon.
• Preferred: Familiarity with OS kernel internals, compiler optimizations, granted patents, or published technical contributions in computer architecture.

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