FPGA Engineer - Quantum Networking (Early Career) at Nu Quantum, Cambridge, England, United Kingdom. A mid-level full time position in the Control team, listed under software engineering.
About the role
We’re looking for an early-career FPGA Engineer, with some relevant experience, including graduates with a strong academic, project or placement background in electronic engineering, computer engineering, embedded systems or a related discipline. Professional FPGA experience is not essential. We’re particularly interested in candidates who can demonstrate hands‑on experience through university projects, internships, placements, personal projects or previous roles. Ideally you will have experience using Xilinx FPGAs and Zynq/Ultrascale SoCs. In this role, you will work with a multidisciplinary team to implement and debug real‑time control systems for quantum networking applications. You will work closely with software and electronics engineers, and AMO physicists to bring‑up and deploy multi‑node quantum networking systems. As a member of the Control team, you will be responsible for developing and supporting our current hardware platforms, which includes the Artiq control system with the Sinara family of hardware, while also contributing to our next generation platform based on CERN’s White Rabbit technology. This is a hands‑on role where you will get to contribute to the development of cutting edge quantum networking infrastructure.
Desirable Skills (nice to have but not required)
These are not expected for a graduate or early‑career candidate, but would be advantageous:
- Experience in low latency and/or real‑time systems.
- Experience debugging Arm or RISC‑V CPU subsystems with GDB, debuggers and trace tools.
- Experience writing embedded C or Rust.
- Verification using Cocotb and/or SystemVerilog, the use of SVAs within verification testbenches and Formal workflows.
- Experience with RF signal generation and processing, including the use of Direct Digital Synthesis (DDS) frequency synthesis techniques, RF communication protocols and modulation techniques.
Responsibilities
- Design, develop, and verify RTL code in SystemVerilog, Verilog, VHDL and/or Migen for Xilinx Zynq and Ultrascale devices.
- Design, develop, and verify Embedded code in C/Rust.
- Develop, debug and verify real‑time control systems using ARTIQ Sinara hardware.
- Collaborate with senior engineers to develop and verify hardware subsystems.
- Contribute to the development of debugging tools to provide in‑system debug visibility of real‑time systems.
- Contribute to design documentation, test plans and technical reports.
- Contribute to automation of tool flows, CI/CD pipelines and automated release flows.
- Collaborate with physicists, optical engineers, hardware and software engineers to define requirements, capture specifications and design appropriate solutions.
Requirements
- A foundational understanding of digital design and RTL principles, with some experience using SystemVerilog, Verilog and/or VHDL.
- Experience with, or a strong understanding of, FPGA development, ideally with Xilinx or Altera devices.
- Familiarity with hardware interfaces and communication protocols such as SPI, I2C and Ethernet.
- Some experience developing and testing digital designs, including the use of testbenches and simulation.
- An understanding of concepts such as clock‑domain crossing (CDC), synthesis and timing.
- Experience with a scripting language, preferably Python.
- Strong written and verbal communication skills, with an ability to document technical work clearly.
- Curiosity, initiative and enthusiasm for learning new concepts, tools and technologies.
Benefits
- Flexible working options
- Group DIS cover (4 x salary)
- 1 month paid Sabbatical after 4 years of service
- Generous Employee Referral Scheme
- Private Medical and Dental Cover (With Vitality and Bupa)
- On‑site gym membership
- Cycle scheme
- Refreshments, including fruit and beverages, are available in the office.
- 28 days annual leave, including a 3‑day company shutdown period + UK Public Holidays
- Option to purchase up to 5 days holiday per year
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FPGA Engineer - Quantum Networking (Early Career) in Cambridge employer: Entangled Future
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