Empiric is seeking 5+ ASIC Verification Engineers for a global semiconductor manufacturing project. You will drive verification strategy, build advanced UVM/SystemVerilog testbenches, and own verification plans for SoC/IP blocks.
The role is based in Bristol or Cambridge with a 12-month rolling contract and a start in December. You should bring strong UVM/SystemVerilog expertise, experience with constrained-random stimulus, coverage-driven verification, and good collaboration with RTL teams to
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Senior ASIC Verification Engineer — SystemVerilog/UVM Expert employer: Empiric
Empiric stands out as an exceptional employer, offering a clear six-month roadmap for career progression and the opportunity to work with a globally recognised brand in technology recruitment. With a supportive work culture that prioritises employee growth and a commitment to excellence, you will thrive in an environment that values your contributions and fosters professional development.
