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- Tasks: Join a cutting-edge SoC team to develop innovative ASICs and learn from industry experts.
- Company: Leading semiconductor company with a focus on multi-discipline collaboration.
- Benefits: Competitive salary, bonuses, hybrid working, and extensive training opportunities.
- Why this job: Make an impact in the tech industry while growing your skills and career.
- Qualifications: Experience in digital ASIC design and verification, with a passion for learning.
- Other info: Dynamic environment with mentorship from top engineers and international project collaboration.
The predicted salary is between 40000 - 104000 ÂŁ per year.
Due to our continued growth, our semiconductor client is looking for a Formal Verification Engineer to join their cutting‑edge SoC team in the development of ASICs. The successful candidate will be working with experts in different aspects of SoC development on state‑of‑the‑art projects. You will be given the opportunity to undertake role‑specific training to further develop your knowledge, experience and career development. The successful candidate will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry‑renowned Senior Director who has built and established many multi‑discipline teams throughout their career and has enjoyed major success. This team is going to be a pure multi‑discipline team which can tackle any issue that comes their way and become some of the industries’ most well‑rounded engineers. This is a fantastic opportunity for an engineer with 5yrs–15+ years’ experience in the industry.
Formal Verification Engineers Expected Contributions
- Mentoring from principal & distinguished engineers.
- Opportunity to become a mentor to your colleagues.
- Understanding of different parts of the design & verification cycle.
- Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. SystemVerilog, UVM, Formal).
- Working on high volume data centre & enterprise products used by industry leading companies.
- Experience of working on projects with teams located internationally.
Formal Verification Essential Qualifications and Skills
- Digital ASIC design and verification experience.
- Experience of Formal Verification (Jasper Gold or VC_Formal).
- Practical experience or desire to learn: Translating design requirements into RTL.
- Deriving functional requirements for verification.
- SystemVerilog UVM test benches.
- Scripting languages & REST APIs (e.g. Perl / Python / TCL).
- Team player with good verbal and written communication skills.
Formal Verification Desirable Skills
- Experience using SV UVM 1800.2.
- Familiarity with C / C++.
- Experience with any of the following storage interfaces: SAS, PCIe, NVMe (preferred) or SATA.
Salary and Package
- Competitive Salaries ranging from £50,000 – £130,000 (depending on level and experience).
- 10‑20% bonus (based on company and individual performance).
- 25 days holiday + 8 days bank holiday per year.
- 3 days a week on site hybrid working.
- Pension (matched group pension up to 8%).
- Life assurance.
- Income protection.
- Private medical.
- Employee supported volunteering.
- Employee assistance program for health wellbeing, financial services, legal services, etc.
- Training and development.
- Visa sponsorship available.
- Relocation support (if required).
My client can offer a 3-stage process consisting of a 1st stage video call, 2nd stage video call and a 3rd stage on‑site interview (meet the team and site tour). This process can be completed within 2‑3 weeks (based on availability).
Formal Verification Engineer in Oxford employer: Elite People Partners Ltd
Contact Detail:
Elite People Partners Ltd Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Formal Verification Engineer in Oxford
✨Tip Number 1
Network like a pro! Reach out to your connections in the semiconductor industry, especially those who might know about opportunities in formal verification. A friendly chat can sometimes lead to job openings that aren't even advertised.
✨Tip Number 2
Prepare for those interviews! Brush up on your knowledge of ASIC design and verification, and be ready to discuss your experience with EDA tools. Practising common interview questions can help you feel more confident when it’s your turn to shine.
✨Tip Number 3
Show off your skills! If you have any projects or contributions to open-source that relate to formal verification, make sure to highlight them. This is your chance to demonstrate your expertise and passion for the field.
✨Tip Number 4
Don’t forget to apply through our website! We’ve got loads of opportunities waiting for talented engineers like you. Plus, applying directly can sometimes give you an edge over other candidates.
We think you need these skills to ace Formal Verification Engineer in Oxford
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Formal Verification Engineer role. Highlight your experience with ASIC design and verification, and don’t forget to mention any relevant tools or languages you’ve worked with, like SystemVerilog or UVM.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're passionate about formal verification and how your skills align with our cutting-edge projects. Keep it concise but impactful!
Show Off Your Team Spirit: We love team players! In your application, mention any experiences where you collaborated with others, especially in multi-discipline teams. This will show us you’re ready to tackle challenges together.
Apply Through Our Website: Don’t forget to apply through our website! It’s the best way for us to receive your application and ensures you’re considered for this fantastic opportunity. We can’t wait to see what you bring to the table!
How to prepare for a job interview at Elite People Partners Ltd
✨Know Your Stuff
Make sure you brush up on your digital ASIC design and verification knowledge. Familiarise yourself with tools like Jasper Gold or VC_Formal, and be ready to discuss your experience with SystemVerilog and UVM test benches. The more you know, the more confident you'll feel!
✨Show Your Passion for Learning
This role is all about growth and learning new skills. Be prepared to talk about how you've embraced learning in the past, whether it's picking up a new scripting language or diving into DevOps. Highlight your eagerness to expand your expertise beyond just formal verification.
✨Communicate Clearly
As a team player, good communication is key! Practice explaining complex concepts in simple terms, as you might need to mentor others or collaborate with international teams. Clear communication can set you apart from other candidates.
✨Prepare for the Team Dynamics
Since you'll be working in a multi-discipline team, think about how you can contribute to tackling challenges together. Prepare examples of past teamwork experiences and how you’ve successfully collaborated with others to solve problems. This will show that you're not just a great engineer, but also a great colleague!
