ASIC Design Verification Engineer – AI Accelerator / SoC

We are seeking a motivated and experienced

ASIC Design Verification Engineer to contribute to the functional verification of next-generation AI accelerators and high-performance So C subsystems.

The ideal candidate will have strong hands-on experience in digital ASIC functional verification, including verification plan development, System Verilog/UVM testbench creation, test case development, and IP Verification Plan (IVP) execution.

The candidate will work closely with ASIC architects, RTL designers, and system engineers to understand design specifications, develop comprehensive verification environments, identify functional issues, and ensure design correctness throughout the ASIC development lifecycle.

Experience with GPU, NPU, AI accelerator, or complex So C subsystem architectures is highly desirable.

This position focuses on hands-on verification engineering, functional debugging, coverage-driven verification, and delivery of high-quality, production-ready ASIC designs.

Key Responsibilities

• 1. ASIC Functional Verification
• Develop and execute functional verification plans for AI accelerators and complex So C functional blocks.
• Analyze architecture and microarchitecture specifications to identify functional requirements, verification scenarios, corner cases, and potential design risks.
• Translate design specifications into detailed verification plans, test cases, assertions, and coverage models.
• Perform IP-level and subsystem-level functional verification.
• Develop directed and constrained-random test cases to validate functional behavior, interface protocols, and error handling.
• Identify, debug, and resolve functional issues in collaboration with RTL design engineers.
• 2. Testbench Development and Verification Methodology
• Design, develop, and maintain reusable verification environments using System Verilog and Universal Verification Methodology (UVM).
• Develop verification components, including drivers, monitors, agents, sequencers, scoreboards, checkers, and functional coverage collectors.
• Implement constrained-random stimulus generation and coverage-driven verification methodologies.
• Develop and integrate behavioral reference models and verification IP.
• Create assertions and protocol checkers to detect functional and interface violations.
• Maintain and enhance existing verification environments to improve simulation efficiency, reusability, and verification quality.
• 3. Verification Planning and IVP Execution
• Develop detailed IP Verification Plans (IVP) based on functional and microarchitecture specifications.
• Define verification scenarios, test cases, coverage points, and expected results for each functional feature.
• Establish traceability between design requirements, test cases, and functional coverage.
• Execute IVPs through directed testing, constrained-random simulation, and regression testing.
• Develop and maintain automated regression suites.
• Analyze functional coverage, code coverage, and regression results to identify verification gaps.
• Develop additional test cases to improve coverage and address uncovered functional scenarios.
• Document verification progress, test results, functional coverage, and outstanding issues.
• Support verification closure and sign-off activities.
• 4. AI Accelerator and So C Subsystem Verification
• Verify digital datapaths, control logic, memory interfaces, DMA engines, and on-chip interconnects.
• Develop verification scenarios for data movement, arbitration, buffering, flow control, and transaction processing.
• Validate subsystem-level interactions, including reset behavior, error handling, backpressure, and corner-case conditions.
• Verify data integrity and functional correctness across complex processing pipelines.
• Collaborate with architecture and RTL design engineers to understand AI accelerator and So C subsystem functionality.
• Support integration verification of multiple IP blocks within larger So C environments.
• 5. Simulation, Debugging, and Regression
• Run RTL simulations using industry-standard simulators such as Cadence Xcelium, Synopsys VCS, or Siemens Questa.
• Debug RTL and testbench issues using waveform viewers, simulation logs, assertions, and transaction-level analysis.
• Identify root causes of functional failures and collaborate with RTL designers to validate fixes.
• Develop scripts to automate test execution, regression management, and results analysis.
• Analyze simulation failures and distinguish design defects from testbench or environment issues.
• Track verification progress and contribute to functional and code coverage closure.
• Required Qualifications
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

2+ years of hands-on experience in digital ASIC/So C functional verification.

• Strong proficiency in System Verilog and UVM-based verification.
• Experience developing and executing functional verification plans and IP Verification Plans (IVP).
• Hands-on experience in testbench development, including drivers, monitors, scoreboards, checkers, and coverage models.
• Experience with directed testing, constrained-random verification, and regression testing.
• Solid understanding of digital logic, RTL design, finite state machines, pipelining, and interface protocols.
• Experience in IP-level or subsystem-level functional verification.
• Familiarity with RTL simulation and debugging tools, such as Cadence Xcelium, Synopsys VCS, Siemens Questa, or equivalent.
• Experience analyzing simulation waveforms, debugging functional failures, and resolving verification issues.
• Understanding of functional coverage, code coverage, and verification closure methodologies.
• Familiarity with scripting languages such as Python, Tcl, Perl, or shell scripting.
• Strong analytical, debugging, and problem-solving skills.
• Ability to independently develop test cases, debug failures, and execute verification tasks.
• Preferred Qualifications
• Good architecture and microarchitecture knowledge of at least one of the following:
• GPU or parallel computing architectures
• NPU, AI accelerator, or machine learning processor architectures
• Complex So C subsystems, such as memory controllers, DMA engines, interconnect fabrics, or high-performance processing subsystems
• Knowledge of LPDDR memory technologies, particularly LPDDR5/LPDDR5X and LPDDR6, including memory controller functionality and interface verification.
• Knowledge of PCIe, particularly PCIe Gen5/Gen6, including transaction processing, protocol behavior, and verification methodologies.
• Knowledge of chip-to-chip and die-to-die interconnect technologies, including UCIe or other high-speed interconnect protocols.
• Knowledge of formal verification, including formal property checking, assertion-based verification, and formal verification tools.
• Familiarity with System Verilog Assertions (SVA).
• Experience with AMBA AXI/ACE/CHI or other industry-standard So C interconnect protocols.
• Familiarity with No C architectures, cache coherency, and memory subsystem verification.
• Understanding of AI/ML accelerator workloads, including matrix multiplication, tensor operations, and inference processing.
• Experience with C/C++, Python, or MATLAB-based reference models and DPI-C integration.
• Familiarity with hardware/software co-verification, FPGA prototyping, or hardware emulation.
• Knowledge of clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power verification methodologies.
• Experience supporting ASIC tape-out verification and silicon bring-up.
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