Research Associate - Heterogeneous Integration: Systems Architecture and Design

Research Associate - Heterogeneous Integration: Systems Architecture and Design Job Title: Research Associate - Heterogeneous Integration: Systems Architecture and Design Posting Start Date: 18/09/2026 Job Id: 3155 School/Department: Electrical please indicate this in your cover letter. You will join the Microelectronics and Integrated Semiconductor Systems Team within the Quantum and Semiconductor Systems (QSS) Group — one of the UK’s largest and most successful semiconductor research environments. The Team hosts Sheffield’s leadership role for CHIMES², which brings together partner universities including Cambridge, Oxford, Edinburgh, Manchester, Newcastle, Strathclyde, Queen’s University Belfast and King’s College London, alongside the Science and Technology Facilities Council. Industrial partners include, among others, Imec, Arm, Pragmatic, Cadence, Synopsys and Siemens EDA. The CTO Office sits at the centre of the programme’s technical intelligence function; you will collaborate closely with the newly established CHIMES² engineering cohort, though the CTO Office and the engineering team are distinct functions. Why this role is distinctive. It is a national-programme intelligence role. You will lead landscape and roadmap work that directly shapes CHIMES² research priorities, demonstrator projects, and the Design Commons — work with reach across the UK ecosystem, not confined to a single lab. It is a deliberate platform to launch from. The post is designed to let you build a visible, fundable independent research identity and the track record to launch it — whether toward a research fellowship (RAEng, UKRI FLF, MSCA, ERC Starting), a first permanent academic appointment, or a senior role in the national semiconductor ecosystem. The four-year term gives genuine room to figure out which of those is right for you and to become competitive for it. You will be a named representative of CHIMES² externally — at IMAPS, IEEE ECTC, DATE, Hot Chips, TechWorks DESN and equivalent forums — and a named author on Design Commons white papers, capability maps and policy briefings produced from your work. Areas of particular interest System partitioning and chiplet decomposition methodologies; cross-die interface specification frameworks. System-technology co-optimisation (STCO/XTCO) and mission-aware partitioning under power, thermal and security constraints. Front-end and system-level EDA for multi-die design — partition-aware synthesis, architectural exploration, system-level floor planning, cross-die timing, die-to-die interface IP. Chiplet interconnect standards (UCIe, CXL, die-to-die PHY) and interoperability frameworks (3Dblox, OIF). Open Design Commons infrastructure and open-source EDA / RISC-V IP ecosystems. All four cross-cutting constraints — design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS) and design-for-thermal-extraction (DfTh) — span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain. No candidate need span all areas. Strong credibility in logical systems architecture and front-end design is the core requirement; depth in one or more of the complementary areas above is welcomed. We particularly welcome applicants whose work has bridged from adjacent backgrounds — computer architecture, embedded systems, FPGA-based research, accelerator or hardware-software co-design, low-power or sensor or quantum-hardware systems, or high-speed PCB / board-level integration — into circuit, system and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device-physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES² partners (notably Imec), and through national semiconductor programmes. Main duties and responsibilities Technology landscape and roadmap Lead the WP1 logical systems architecture domain landscape activities — structured analysis of the needs of integrators and of those seeking to integrate maturing-TRL device, circuit or interposer propositions — covering system partitioning, chiplet decomposition, cross-die interface specification, and STCO/XTCO approaches across the UK and international HI community. Develop and maintain CHIMES² roadmaps for the logical architecture and front-end design domain, cross-referencing international roadmap assets including IEEE HIR, EU APECS, DARPA CHIPS/NGMM, SRC JUMP 2.0, imec STCO, and interoperability standards (UCIe / 3Dblox / OIF / CXL). Analyse front-end EDA tool gaps for heterogeneous integration — partition‑aware synthesis, multi‑die timing closure, DfT insertion at the chiplet boundary, DfS architectural patterns, power‑intent specification across dies (UPF/CPF), and thermal‑aware floorplanning. Conduct structured gap analysis identifying integration‑specific design challenges underserved by current UK and international R Hybrid and flexible working options considered Duration Fixed term for 48 months (4 years) from start date Line manager Professor John Goodenough, CHIMES² Director / PI Right to work in the UK If you do not currently hold the right to work in the UK, you can find more information here to help determine your visa eligibility. Additional guidance is also available on the UK Visa where it applies, the University will support the postholder through that process. Closing Date :01/11/2026 We are a research university with a global reputation for excellence. Our ideas and expertise change the world for the better, making a real difference to society. We know that when people come together with different views, approaches and insights it can lead to richer, more creative and innovative teaching and research and the highest levels of student experience. Our University Vision ( www.sheffield.ac.uk/vision ) outlines our commitment to building a diverse community of staff and students that recognises and values the abilities, backgrounds, beliefs and ways of living for everyone. The University of Sheffield Western Bank Sheffield S10 2TN #J-18808-Ljbffr