Hardware Engineer, Architect in London

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Most accelerator architecture is refinement: a known base compute architecture, a known programming model, and decades of prior art to lean on. This role is not that. Normal's silicon computes with stochastic analog dynamics in memory, and the architecture that exploits it fully is being discovered alongside the development. As our Silicon Architect, you will own the architecture of its compute blocks: the core decisions that determine how Normal's silicon actually computes, working directly with our Systems Architect, research and engineering leadership, and the AI platform team whose tools you'll use to design it. This is a seat for someone who wants to define structures that no prior art covers, and who has the architecture-to-silicon range to defend them all the way to tapeout.

What You Will Own

• Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation.
• Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against.
• Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints.
• ISA Co-Design: Partner with the compiler lead on ISA co-design. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle.
• Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions need to be answered, and the appropriate platform.
• Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters.

What Makes You a Great Fit

• A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential.
• Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic.
• Fluency moving between algorithm-level analysis and hardware specification.
• Experience with simulation-driven architecture.
• Familiarity with quantization and reduced-precision approaches for inference and their implementation implications.
• Experience writing microarchitecture specifications and working closely with RTL engineers through implementation.
• Proficiency in Python or C++ for performance modeling and analysis, and familiarity with SystemVerilog or equivalent RTL.
• Comfort operating in an environment where the architecture is actively being discovered alongside the work.