ASIC RTL Design & Verification Engineer (UVM)

ASIC RTL Design & Verification Engineer (UVM)

Full-Time 40000 - 55000 £ / year (est.) No working from home possible
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At a Glance

  • Tasks: Design and implement RTL modules for cutting-edge ASIC/SoC projects.
  • Company: Join a leading tech firm focused on innovative chip design.
  • Benefits: Gain hands-on experience with advanced technology and clear career progression.
  • Other info: Dynamic work environment with opportunities for automation and tooling improvements.
  • Why this job: Make a real-world impact while collaborating with top engineers in the field.
  • Qualifications: Bachelor's degree in Engineering and familiarity with Verilog/SystemVerilog.

The predicted salary is between 40000 - 55000 £ per year.

Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

Job Responsibilities:

  • Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
  • Develop and execute verification plans, including testbench development using UVM methodology.
  • Perform functional verification, debugging, and coverage analysis to ensure design correctness.
  • Participate in SoC integration, testability (DFT) design, and overall front-end development flow.
  • Collaborate with architecture, physical design, and software teams to ensure seamless integration.
  • Contribute to automation and tooling improvements using scripting languages.

Job Requirements:

  • Bachelor's degree or above in Electrical Engineering, Computer Engineering, or related fields.
  • Understanding of digital design fundamentals and IC development flow.
  • Familiarity with Verilog/SystemVerilog and basic RTL design concepts.
  • Exposure to verification methodologies (e.g., UVM) is a plus.
  • Basic scripting skills (Python / Shell) preferred.
  • Strong analytical thinking, problem-solving ability, and learning agility.

What They Offer:

  • Opportunity to work on advanced ASIC/SoC projects with real-world impact.
  • Exposure to both design and verification in a full front-end flow.
  • Clear career progression in chip design and verification domains.

ASIC RTL Design & Verification Engineer (UVM) employer: Dada Consultants

Join a forward-thinking company that excels in ASIC and SoC development, offering you the chance to work on cutting-edge projects that make a real-world impact. With a strong emphasis on collaboration and innovation, our work culture fosters continuous learning and professional growth, ensuring clear career progression in the chip design and verification domains. Located in a vibrant tech hub, we provide an environment where your contributions are valued and rewarded, alongside opportunities for skill enhancement through exposure to both design and verification processes.

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Contact Details:

Dada Consultants Recruitment Team

StudySmarter Expert Advice🤫

We think this is how you could land ASIC RTL Design & Verification Engineer (UVM)

Tip Number 1

Network like a pro! Reach out to your connections in the ASIC/SoC field and let them know you're on the lookout for opportunities. You never know who might have a lead or can refer you to a hiring manager.

Tip Number 2

Show off your skills! Create a portfolio showcasing your RTL design projects, verification plans, and any automation tools you've developed. This will give potential employers a tangible sense of what you can bring to the table.

Tip Number 3

Prepare for interviews by brushing up on UVM methodologies and digital design fundamentals. Practice explaining your past projects and how you tackled challenges—this will help you stand out during technical discussions.

Tip Number 4

Don't forget to apply through our website! We regularly update our job listings, and applying directly can sometimes give you an edge. Plus, it shows you're genuinely interested in joining our team!

We think you need these skills to ace ASIC RTL Design & Verification Engineer (UVM)

RTL Design
Verilog
SystemVerilog
UVM
Functional Verification
Debugging
Coverage Analysis

Some tips for your application 🫡

Tailor Your CV:Make sure your CV highlights your experience with RTL design and verification. We want to see how your skills in Verilog/SystemVerilog and UVM can shine through, so don’t hold back on showcasing relevant projects!

Craft a Compelling Cover Letter:Your cover letter is your chance to tell us why you’re the perfect fit for this role. Share your passion for ASIC development and how your background aligns with our needs. Keep it engaging and personal!

Showcase Your Skills:Don’t forget to mention any scripting skills you have, like Python or Shell. We love seeing candidates who can contribute to automation and tooling improvements, so let us know what you’ve done in this area!

Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy!

How to prepare for a job interview at Dada Consultants

Know Your RTL Inside Out

Make sure you brush up on your Verilog and SystemVerilog skills. Be ready to discuss your previous projects where you designed RTL modules, and be prepared to explain your thought process behind the design choices you made.

Master UVM Methodology

Since UVM is a key part of the role, ensure you understand its principles thoroughly. You might be asked to describe how you've implemented UVM in past projects, so have specific examples ready to showcase your experience.

Showcase Your Problem-Solving Skills

Prepare to discuss challenges you've faced during functional verification or debugging. Highlight your analytical thinking and how you approached these problems, as this will demonstrate your ability to tackle real-world issues.

Collaboration is Key

This role involves working with various teams, so be ready to talk about your experience collaborating with architecture, physical design, and software teams. Share examples of how you contributed to seamless integration and any automation improvements you’ve made using scripting languages.