FPGA Design Engineer - Contractor Hardware Engineering · Cottenham

Job Description

We are looking for a hands‑on FPGA Design Engineer to develop high‑reliability digital logic for motorsport engine controllers (ECUs) and power management units (PMUs).

You’ll own RTL design on Intel (Altera) CycloneV FPGA/SoC platforms, integrate with high‑speed I/O, and implement robust inter‑FPGA communications across complex boards.

The Role

• FPGA architecture & RTL design: Specify, implement, and maintain VHDL for control, signal processing, timing, and safety features on CycloneV devices (including SoC variants with HPS integration).
• SoC/HPS integration: IntegrateV SoC (ARM CortexA9 HPS) via Avalon/AXI bridges; define memory‑mapped peripherals, DMA paths, and shared memory for realtime data exchange.
• InterFPGA communications: Design and validate reliable links (e.g., LVDS, custom serial, Auroralike soft links), including CDC management, link bringup, and error detection/correction.
• ECU/PMU features: Implement crank/cam wheel decoding, toothgap detection, phase tracking, and timestamping. PWM/injection/ignition timing blocks with microsecond‑level determinism. Sensor acquisition pipelines (SPI/I²C/UART/ADC interfaces), digital filtering (fixed‑point), diagnostics, and failsafe state machines. PMU switching control, current/voltage monitoring. CAN 2.0B transmit and receive.
• Verification: Build unit and system testbenches.
• Board bringup: Support lab validation with oscilloscopes, logic analysers, JTAG, boundary scan; root‑cause issues across FPGA ↔ MCU/HPS ↔ sensors/actuators.
• Documentation & release discipline: Produce clear specs, design notes, release artifacts; adhere to version control (Git) workflows.
• Cross‑functional delivery: Partner with hardware and embedded software teams to hit milestones under tight timelines.
• Consider the health and safety, environmental and energy impact of all activities.

Compliance & Data Protection

• Support the Company’s compliance with the UK General Data Protection Regulation (UK GDPR) and the Data Protection Act 2018 by following company policy and best practice.

Candidate Profile

• Demonstrable FPGA development with Intel (Altera) CycloneV (including SoC/HPS).
• Strong RTL skills (VHDL/Verilog/SystemVerilog) and Quartus Prime, TimeQuest.
• Proven interFPGA communication design (LVDS/serial links/high‑speed SPI) and CDC best practices.
• Experience integrating fabric with processors via Avalon/AXI, memory‑mapped interfaces, DDR3/SRAM controllers.
• Solid verification skills and hands‑on lab bringup experience.
• Version control (Git) is essential: branching, code reviews, tags/releases, submodules/IP management.
• Ability to read schematics, collaborate with hardware teams, and work to tight motorsport timelines.