Lead Physical Design Engineer, ASIC/AI/CPU Layout in London

Lead Physical Design Engineer, ASIC/AI/CPU Layout in London

London Full-Time 60000 - 80000 £ / year (est.) No home office possible
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At a Glance

  • Tasks: Design advanced ASIC/AI/CPU chips and manage the entire layout process.
  • Company: Join a leading consortium focused on clinical research and innovation.
  • Benefits: Competitive salary, innovative projects, and opportunities for professional growth.
  • Other info: Dynamic team environment with a focus on innovation and collaboration.
  • Why this job: Work with cutting-edge technology and contribute to groundbreaking advancements in healthcare.
  • Qualifications: Strong understanding of IC development and physical design experience.

The predicted salary is between 60000 - 80000 £ per year.

Consortium for Clinical Research and Innovation Singapore is looking for a Physical Designer Engineer in Greater London. The role involves the physical design of advanced process digital ASIC/AI/CPU chips and includes responsibilities such as:

  • Back-end physical implementation from gate-level netlist to GDSII
  • Layout design of chips
  • Signoff processes

Ideal candidates should have a good understanding of IC development. This position offers an opportunity to work with cutting-edge technologies in advanced packaging.

Lead Physical Design Engineer, ASIC/AI/CPU Layout in London employer: Consortium for Clinical Research and Innovation Singapore

At the Consortium for Clinical Research and Innovation Singapore, we pride ourselves on being an excellent employer by fostering a collaborative and innovative work culture that encourages professional growth. Located in Greater London, our team enjoys access to cutting-edge technologies and advanced packaging, along with comprehensive benefits and opportunities for career advancement in the rapidly evolving field of ASIC/AI/CPU design.
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Contact Detail:

Consortium for Clinical Research and Innovation Singapore Recruiting Team

StudySmarter Expert Advice 🤫

We think this is how you could land Lead Physical Design Engineer, ASIC/AI/CPU Layout in London

✨Tip Number 1

Network like a pro! Reach out to professionals in the ASIC/AI/CPU design field on LinkedIn or at industry events. We can’t stress enough how valuable personal connections can be in landing that dream job.

✨Tip Number 2

Show off your skills! Create a portfolio showcasing your previous projects and designs. This is your chance to demonstrate your expertise in physical design and IC development, so make it shine!

✨Tip Number 3

Prepare for interviews by brushing up on technical questions related to back-end physical implementation and layout design. We recommend practising with friends or using mock interview platforms to boost your confidence.

✨Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets noticed. Plus, we love seeing candidates who are proactive about their job search!

We think you need these skills to ace Lead Physical Design Engineer, ASIC/AI/CPU Layout in London

Physical Design
ASIC Design
AI Chip Layout
CPU Layout
Back-end Physical Implementation
Gate-level Netlist
GDSII
Layout Design
Signoff Processes
IC Development
Advanced Packaging
Understanding of Cutting-edge Technologies

Some tips for your application 🫡

Tailor Your CV: Make sure your CV highlights your experience in physical design and ASIC/AI/CPU layout. We want to see how your skills align with the role, so don’t be shy about showcasing relevant projects!

Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about physical design and how your background makes you a perfect fit for our team. Keep it engaging and personal.

Showcase Your Technical Skills: Don’t forget to mention your technical expertise in IC development and any tools you’ve used for back-end physical implementation. We love seeing candidates who are well-versed in the latest technologies!

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy!

How to prepare for a job interview at Consortium for Clinical Research and Innovation Singapore

✨Know Your ASIC Fundamentals

Make sure you brush up on your knowledge of ASIC design principles, especially the back-end physical implementation process. Be ready to discuss your experience with gate-level netlists and GDSII layouts, as this will show your technical expertise.

✨Showcase Your Layout Design Skills

Prepare to talk about specific projects where you've designed chip layouts. Bring examples that highlight your problem-solving skills and creativity in layout design, as well as any challenges you faced and how you overcame them.

✨Understand the Signoff Process

Familiarise yourself with the signoff processes involved in physical design. Be prepared to explain how you ensure that designs meet all specifications and standards before finalisation, as this is crucial for the role.

✨Stay Updated on Advanced Packaging Technologies

Since the position involves cutting-edge technologies, do some research on the latest trends in advanced packaging. Being able to discuss these innovations will demonstrate your enthusiasm for the field and your commitment to staying current.

Lead Physical Design Engineer, ASIC/AI/CPU Layout in London
Consortium for Clinical Research and Innovation Singapore
Location: London

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