Senior Physical Design Engineer

Senior Physical Design Engineer

Full-Time 60000 - 80000 € / year (est.) Home office (partial)
Cirrus Logic

At a Glance

  • Tasks: Implement cutting-edge mixed-signal SOCs and collaborate with a dynamic design team.
  • Company: Join Cirrus Logic, a leader in mixed-signal processing with an award-winning culture.
  • Benefits: Enjoy a hybrid work model, competitive salary, and a supportive work environment.
  • Other info: Exciting opportunities for career growth in a diverse and innovative team.
  • Why this job: Make a real impact in technology while growing your career in an inclusive workplace.
  • Qualifications: Degree in Electrical Engineering and experience in Physical Design required.

The predicted salary is between 60000 - 80000 € per year.

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

We have an exciting opportunity for a talented Senior Physical Design Engineer to join our growing team in Edinburgh. In this role, you will have the opportunity to implement industry leading mixed-signal SOCs for consumer markets and become part of an organisation operating at the forefront of cutting‑edge technology. This role would suit a candidate with an ability to work independently and as part of a wider design team.

Responsibilities
  • All aspects of RTL to GDS2 physical implementation for complex ASIC projects.
  • Working with Digital Design, Analogue Layout and DFT teams to ensure on time and high-quality results.
  • Participating in project scoping and planning activities.
  • Developing P&R methodologies for continuous improvement.
Required Skills and Qualifications
  • Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a Physical Design position.
  • Wide experience with industry standard EDA tools for digital implementation and signoff, and the ideal candidate should be familiar with:
    • Synopsys Design Compiler and Primetime
    • Cadence Innovus, Voltus and Conformal
  • Hands‑on working knowledge of deep sub‑micron ASIC implementation and expertise in areas such as:
    • RTL synthesis
    • Timing constraint debug and development
    • Floorplanning and power planning
    • Clock tree synthesis
    • P&R optimisation, timing closure and ECO implementation
    • Static timing analysis
    • Logical Equivalence Checks
    • Power and EMIR analysis
  • Proven responsibility for full design flow to design closure and tapeout.
  • Knowledge of automating and advancing flows with proficiency in scripting.
  • Ability to perform debug and analysis of designs, libraries, and technology files.
  • Good communication and excellent collaboration skills.

This position is based in our Edinburgh office, UK. This is a hybrid position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic.

At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.

Senior Physical Design Engineer employer: Cirrus Logic

Cirrus Logic is an exceptional employer that fosters a vibrant and inclusive work culture, where innovation thrives and employees are empowered to grow their careers. Located in the heart of Edinburgh, our hybrid work model offers flexibility while engaging in cutting-edge technology projects that impact top consumer brands. With a commitment to community engagement and employee satisfaction, Cirrus Logic provides a rewarding environment for talented individuals seeking meaningful contributions in the field of mixed-signal processing.

Cirrus Logic

Contact Detail:

Cirrus Logic Recruiting Team

StudySmarter Expert Advice🤫

We think this is how you could land Senior Physical Design Engineer

Tip Number 1

Network like a pro! Reach out to current or former employees at Cirrus Logic on LinkedIn. A friendly chat can give you insider info and maybe even a referral, which can really boost your chances.

Tip Number 2

Prepare for the interview by brushing up on your technical skills. Make sure you can talk confidently about RTL to GDS2 implementation and your experience with EDA tools. We want to see your passion for mixed-signal SOCs!

Tip Number 3

Show off your collaboration skills! Cirrus Logic values teamwork, so be ready to share examples of how you've worked with cross-functional teams in the past. Highlighting your communication prowess can set you apart.

Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets seen. Plus, it shows you’re genuinely interested in joining our awesome team at Cirrus Logic.

We think you need these skills to ace Senior Physical Design Engineer

RTL to GDS2 physical implementation
Digital Design collaboration
Analogue Layout collaboration
DFT team collaboration
P&R methodologies development
Synopsys Design Compiler
Primetime

Some tips for your application 🫡

Tailor Your CV:Make sure your CV is tailored to the Senior Physical Design Engineer role. Highlight your experience with EDA tools and ASIC projects, and don’t forget to mention any relevant qualifications. We want to see how your skills align with what we’re looking for!

Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you’re passionate about this role and how you can contribute to our team at Cirrus Logic. Keep it concise but engaging – we love a good story!

Show Off Your Projects:If you’ve worked on any impressive projects, make sure to include them in your application. We’re keen to see examples of your work, especially those that demonstrate your expertise in physical design and collaboration with other teams.

Apply Through Our Website:We encourage you to apply through our website for a smoother process. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it shows you’re serious about joining our awesome team!

How to prepare for a job interview at Cirrus Logic

Know Your Tools Inside Out

Make sure you’re well-versed in the industry-standard EDA tools mentioned in the job description, like Synopsys Design Compiler and Cadence Innovus. Brush up on your knowledge of RTL synthesis and static timing analysis, as these will likely come up during technical discussions.

Showcase Your Problem-Solving Skills

Prepare to discuss specific challenges you've faced in previous projects, especially those related to P&R optimisation and timing closure. Use the STAR method (Situation, Task, Action, Result) to structure your answers and highlight your contributions.

Emphasise Collaboration

Cirrus Logic values teamwork, so be ready to talk about how you’ve worked with cross-functional teams in the past. Share examples of how you’ve collaborated with digital design, analogue layout, and DFT teams to achieve project goals.

Cultural Fit Matters

Familiarise yourself with Cirrus Logic’s culture of inclusion and fairness. Be prepared to discuss how you can contribute to a positive work environment and engage with the community, as this aligns with their core values.