Senior DFT Engineer - SoC ATPG & Scan

A leading semiconductor company in the United Kingdom is seeking a DFT Engineer with experience in implementing DFT on large SoC designs. Candidates should be proficient in ATPG implementations, particularly with Mentor Tessent TestKompress. Knowledge of JTAG/IJTAG and silicon bring-up experience is highly valued. This role offers an opportunity to work in a dynamic environment focusing on cutting-edge technologies. #J-18808-Ljbffr