Senior DFT Engineer - SoC ATPG & Scan in London
Senior DFT Engineer - SoC ATPG & Scan

Senior DFT Engineer - SoC ATPG & Scan in London

London Full-Time 48000 - 72000 Β£ / year (est.) No home office possible
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At a Glance

  • Tasks: Implement DFT on large SoC designs and work with cutting-edge technologies.
  • Company: Leading semiconductor company in the UK with a focus on innovation.
  • Benefits: Competitive salary, dynamic work environment, and opportunities for professional growth.
  • Why this job: Join a team that shapes the future of technology and makes a real impact.
  • Qualifications: Experience in DFT, ATPG implementations, and knowledge of JTAG/IJTAG.
  • Other info: Exciting projects and a collaborative atmosphere await you.

The predicted salary is between 48000 - 72000 Β£ per year.

A leading semiconductor company in the United Kingdom is seeking a DFT Engineer with experience in implementing DFT on large SoC designs. Candidates should be proficient in ATPG implementations, particularly with Mentor Tessent TestKompress. Knowledge of JTAG/IJTAG and silicon bring-up experience is highly valued. This role offers an opportunity to work in a dynamic environment focusing on cutting-edge technologies.

Senior DFT Engineer - SoC ATPG & Scan in London employer: Chipright

As a leading semiconductor company in the United Kingdom, we pride ourselves on fostering a collaborative and innovative work culture that empowers our employees to excel in their roles. With a strong focus on professional development, we offer numerous growth opportunities and access to the latest technologies, ensuring that our team remains at the forefront of the industry. Join us to be part of a dynamic environment where your contributions are valued and rewarded.
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Contact Detail:

Chipright Recruiting Team

StudySmarter Expert Advice 🀫

We think this is how you could land Senior DFT Engineer - SoC ATPG & Scan in London

✨Tip Number 1

Network like a pro! Reach out to your connections in the semiconductor industry, especially those who work with DFT and SoC designs. A friendly chat can lead to insider info about job openings that might not even be advertised yet.

✨Tip Number 2

Show off your skills! Prepare a portfolio or a presentation that highlights your experience with ATPG implementations and tools like Mentor Tessent TestKompress. This will give you an edge during interviews and show that you're ready to hit the ground running.

✨Tip Number 3

Practice makes perfect! Brush up on your JTAG/IJTAG knowledge and silicon bring-up experience. You never know when a technical question might pop up, so being well-prepared can really impress your interviewers.

✨Tip Number 4

Apply through our website! We make it super easy for you to submit your application directly. Plus, it shows us that you're genuinely interested in joining our dynamic team working on cutting-edge technologies.

We think you need these skills to ace Senior DFT Engineer - SoC ATPG & Scan in London

DFT Implementation
ATPG Implementations
Mentor Tessent TestKompress
JTAG/IJTAG Knowledge
Silicon Bring-Up Experience
Large SoC Design Experience
Dynamic Environment Adaptability
Cutting-Edge Technology Familiarity

Some tips for your application 🫑

Tailor Your CV: Make sure your CV highlights your experience with DFT on large SoC designs. We want to see your proficiency in ATPG implementations and any hands-on work you've done with Mentor Tessent TestKompress.

Showcase Relevant Skills: Don’t forget to mention your knowledge of JTAG/IJTAG and any silicon bring-up experience. These are key skills for us, so make them stand out in your application!

Craft a Compelling Cover Letter: Use your cover letter to tell us why you’re passionate about working in a dynamic environment with cutting-edge technologies. Share specific examples of your past work that relate to the role.

Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you don’t miss any important updates from our team!

How to prepare for a job interview at Chipright

✨Know Your DFT Inside Out

Make sure you brush up on your knowledge of Design for Test (DFT) principles, especially as they relate to large SoC designs. Be ready to discuss your experience with ATPG implementations and how you've used Mentor Tessent TestKompress in past projects.

✨Showcase Your JTAG/IJTAG Skills

Since knowledge of JTAG/IJTAG is highly valued, prepare to talk about specific instances where you've applied these skills. Think of examples that highlight your problem-solving abilities during silicon bring-up processes.

✨Demonstrate Your Passion for Cutting-Edge Tech

This role is all about working with the latest technologies, so express your enthusiasm for innovation in the semiconductor industry. Share any recent projects or technologies you've explored that align with the company's focus.

✨Ask Insightful Questions

Prepare a few thoughtful questions about the company’s current projects or future directions in DFT. This shows your genuine interest in the role and helps you gauge if the company is the right fit for you.

Senior DFT Engineer - SoC ATPG & Scan in London
Chipright
Location: London
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  • Senior DFT Engineer - SoC ATPG & Scan in London

    London
    Full-Time
    48000 - 72000 Β£ / year (est.)
  • C

    Chipright

    50-100
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