We are looking for a DFT Engineer with the following skill sets:
- Experience implementing DFT on large SoC designs
- ATPG implementations using Mentor Tessent TestKompress and a fully hierarchical strategy
- Implementation of Scan for stuck-at and At-speed ATPG
- Experience with JTAG / IJTAG
- Silicon Bring up experience
- ATPG Architecture using Mentor Graphics Flow
Principal IC Digital Design Recruitment Specialist
natalia.bisaga@chipright.com
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Contact Detail:
Chipright Recruiting Team