Capgemini Engineering seeks an Expert Front-End ASIC RTL Designer to join a team working on advanced semiconductor technologies. You will design, develop and debug ASIC IPs, collaborating across design, verification and software teams to deliver high-quality SoCs.
The role involves RTL design in Verilog/SystemVerilog/VHDL, IP integration at the SoC level, and adherence to DFT, CDC, RDC, Lint, and UPF guidelines in a dynamic engineering environment.
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Senior ASIC RTL Front-End Engineer — SoC Innovation employer: Capgemini Engineering
Capgemini Engineering is an exceptional employer, offering a dynamic work environment in Portsmouth where innovation meets quality excellence. Employees benefit from a culture of collaboration and continuous improvement, with ample opportunities for professional growth through hands-on experience in high-reliability engineering sectors. Join us to make a meaningful impact while working alongside industry experts dedicated to driving quality and operational success.
