Electronic FPGA Engineer HUBER+SUHNER Polatis

Your tasks include designing and implementing FPGA logic in VHDL for Xilinx Artix-7 devices using Vivado, adhering to coding standards and design reviews. You will develop finite state machines to control and sequence hardware interfaces and protocols reliably, create low-level driver logic for I²C, SPI (and other simple serial interfaces), including initialisation, transaction handling, and error conditions. Additionally, you will write and maintain test benches (self-checking where practical), conduct functional and timing simulations, and document verification results.

Other responsibilities involve performing hardware bring-up and validation, including lab testing, measurements, and iterative debug; collaborating on board-level constraints and interface timing. You will manage constraints (XDC), clocking, resets, and CDC analysis; achieve timing closure and generate production-ready bitstreams. Contributing to requirements capture, architecture design, module specifications, and DFT/DFM considerations for FPGA-based systems is also part of your role.

You will maintain configuration management (SVN), branching/release processes, and traceability to requirements. Producing and maintaining technical documentation such as design descriptions, registers/interfaces, test procedures, and change logs is essential. Participation in design and code reviews, supporting system integration, and assisting production/field teams with issue triage are expected. Furthermore, you will support continuous improvement of FPGA design flows, test coverage, and automation (e.g., Tcl/Python scripts).

Your profile should include a degree or equivalent experience in Electronic/Electrical Engineering, Computer Engineering, or a related discipline. Strong hands-on experience with VHDL for FPGA design and verification is required, along with proven experience targeting Xilinx Artix-7 families and confidence using Vivado (project setup, constraints, synthesis, place & route, timing closure, bitstream generation).

Additionally, you should have the ability to design deterministic finite state machines (FSMs) for control/driver logic, experience implementing and validating low-level embedded interfaces: I²C, SPI, UART (desirable), including bus arbitration, timing, and protocol edge cases. Competence in writing self-checking test benches and performing simulation (e.g., using Vivado simulator) is necessary.

Experience testing on hardware, bringing up boards, using logic analysers/oscilloscopes, debugging timing/constraint issues, and validating firmware in-system is important. Understanding of timing constraints (XDC), clock domain crossing (CDC), metastability, resets, and synchronous design best practices is expected. Familiarity with version control (e.g., SVN) is also beneficial.

Typically, you should have 3+ years in FPGA development within a product or R&D environment (or demonstrable equivalent). A track record of delivering FPGA features/modules from requirements through to validated hardware is essential. Experience collaborating with electronics engineers and embedded software engineers for system integration is required.

You should be a clear communicator with strong documentation habits (design specs, interface descriptions, test plans, release notes), a methodical problem-solver with attention to detail, and able to work independently and in cross-functional teams. An ownership mindset with a focus on reliability, maintainability, and testability is crucial.