Senior/Principal Packaging Engineer in Cambridge

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Senior Packaging / Principal Packaging Engineer (GaN)

Team – R&D Engineering
Location – Cambridge, UK
Contract – Full-time, Permanent

About CGD

A spin-out of Cambridge University, Cambridge GaN Devices (CGD) is a fabless semiconductor company developing energy‑efficient GaN‑based power devices to enable greener electronics. The global power semiconductor market is expected to exceed $50bn. CGD has secured multi‑million seed funding and Series A and B private investments, and has four projects funded by iUK, BEIS, and the EU (Penta). The team’s technical and commercial expertise, combined with a strong track record in the power‑electronics market, drives early traction of our proprietary technology.

Why Work for CGD

We champion commitment, celebrate empowerment, and reward the brave. We seek change‑makers passionate about power semiconductors who explore unconventional ways to meet our green agenda. CGD offers a relaxed yet productive environment where all are respected and experienced professional growth. If you thrive on innovation, challenge, and growth, we want to hear from you.

The Opportunity

CGD is looking for a Senior Packaging or Principal Packaging Engineer (depending on experience) to join our growing engineering team. Reporting directly to the Director of Engineering, you will drive the packaging solutions for CGD’s GaN power products and collaborate closely with the GaN chip design, Operations, and Application Engineering teams across the globe.

Main Responsibilities

• Lead the technical development of high‑performance, high‑density semiconductor packaging solutions for CGD GaN power products
• Collaborate with internal (GaN chip design, Application Engineering, Operations) and external stakeholders (packaging partners) in the UK and overseas
• Survey market for suitable packaging technologies to support the product roadmap
• Drive package technology developments with suppliers to differentiate CGD products
• Conduct multiphysics simulations (finite element modelling) to analyse package and system‑level thermal performance, parasitic extraction, current spreading, electromagnetic fields and thermo‑mechanical stress
• Design wirebond, flip‑chip and embedded semiconductor packages, including wafer back‑end process modifications, to meet form‑factor, electrical and thermal goals
• Contribute to development and enhancement of design process, tools and methodologies to streamline design flow for first‑time, right‑first‑time solutions
• Support semiconductor packaging verification and qualification tests, including board‑level reliability and thermal characterisation
• Build professional networks to stay current with state‑of‑the‑art packaging and process development in industry and academia
• Carry out first‑article inspection and failure analysis in Cambridge labs and with external partners
• Provide packaging‑related resources to Applications Engineering and customers (outline drawings, thermal models, PCB footprints, technical notes)
• Significantly contribute to the CGD product roadmap development
• Collaborate on power module designs for higher‑power demonstrations of CGD ICeGaN products with partners

Requirements

Skills and Experience

Suitable candidates will have a background in designing and developing semiconductor packages. Experience in power products or GaN design is advantageous but not required. A strong mechanical or electromechanical engineering background with 3‑D drawing, thermal, and electromagnetic expertise is also desirable.

Essential

• Bachelor’s degree or higher in Engineering, Physics, Materials Science or related field
• Solid experience with 3‑D multiphysics simulation (e.g., COMSOL, ANSYS) for thermal, electrical and stress analysis by finite element modelling
• Experience producing designs according to supplier design rules using a modern 3‑D CAD tool (e.g., SolidWorks, Fusion360, AutoCAD)
• Solid understanding or experience with thermal characterisation of semiconductor packages
• Good experience with semiconductor packaging qualification tests such as TCoB, MSL, TC, HAST and HTS following JEDEC, IPC, MIL, AEC‑Q100 standards
• Proficient at leading cross‑functional teams inside the company and with external partners, including overseas teams
• Strong problem‑solving skills and familiarity with methodologies such as 8D, DOE, Fishbone diagrams
• Ability to manage own tasks and deliver results on time
• Experienced in preparing, presenting and reporting results to team members, external partners and stakeholders

Desirable

• Experience in designing and manufacturing high‑volume semiconductor packages, including overseas assembly houses
• In‑depth knowledge of power semiconductor packaging technologies (die‑attach, Ag‑sintering, flip‑chip, wire bonding, PCB embedding, chip metallisation)
• Track record of designing and simulating semiconductor packages for voltages >100 V, ideally for GaN power devices
• Experience with electromagnetic finite‑element modelling
• Experience selecting and analysing semiconductor packaging test methods (CSAM, X‑ray, shear tests, CT, EDX, EMMI)
• Formal project management training and experience, usage of JIRA for task management and issue tracking
• Experience managing public‑funded collaborative projects

Benefits

• Excellent salary
• Share option scheme available
• Pension scheme (6% company contribution)
• Life assurance (3× salary)
• BUPA Private Medical Insurance
• BUPA Cash Plan (Level 3)
• Flexible working options (location and times)
• Annual leave allowance of 33 days (including bank holidays)
• Training and development
• Electric car scheme
• Cycle‑to‑work scheme
• IP bonus scheme
• Involvement in collaborative projects and grants with University of Cambridge and partners
• Recruitment referral bonus
• Regular social events (company lunches, annual summer party, Christmas party, team‑building and wellbeing activities)

We Believe in Equal Opportunities

We are committed to providing equal opportunities to all current and prospective employees regardless of age, disability, sex, sexual orientation, pregnancy and maternity, race or ethnicity, religion or belief, gender identity, or marriage and civil partnership. From application to interview, inclusion is at the heart of all we do.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Engineering and Information Technology

Industries

Semiconductor Manufacturing