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- Tasks: Develop and validate cutting-edge SoC reference systems for high-performance applications.
- Company: Join Cadence, a leader in electronic design with over 30 years of innovation.
- Benefits: Enjoy a full-time role with opportunities for growth and a diverse workplace culture.
- Why this job: Make an impact in technology while working on exciting projects in AI and automotive sectors.
- Qualifications: Requires a degree in Electronic Engineering/Computer Science and relevant experience in ASIC design.
- Other info: Cadence values diversity and is committed to equal employment opportunities.
The predicted salary is between 48000 - 72000 £ per year.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Sr Principal Verification Engineer
Location: Cambridge
Reports to: Sr Design Engineering Architect
Job Overview
The Cadence Computer Systems Group (CSG) develops and licenses IP for system designs. This includes CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping billions of chips annually using our components.
The CSG Central Applications Engineering team seeks an experienced and talented SoC design engineer to join a new team for CSG systems. In this role, you will be responsible for developing and validating reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications.
This is a technically rewarding role with high visibility within the organization. The team is responsible for supporting customers of CSG subsystems. The group will also implement reference designs on emulation systems and support applications for product demonstrations.
This role requires extensive experience IP integration and implementing SoC and compute-based systems. You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities of CSG subsystems and components.
Responsibilities
- Develop, implement, and debug SoC reference systems.
- Integrate compute, memory and interface IP in system designs.
- Analyse IP products and implementation flows.
- Identify gaps and work with development teams to improve products.
- Develop collateral, and training material for CSG system customers.
- Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.
- Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team’s workflows.
Requirements
- BS in Electronic Engineering/Computer Science with 8+ years work experience, or MS in EE/CS with 4+ years’ experience.
- Must have at least 3 years of experience in ASIC design, integration, or verification.
- Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.
- Expertise in Verilog/System Verilog for coding and verification.
- Proficiency in RTL design techniques, including synthesis, timing closure, and verification.
- Experience in using UVM for functional verification of ASIC designs.
- Experience with EDA tools like Cadence and Synopsys for design simulation and verification.
- Extensive experience with FPGA emulation, design tools, and verification.
Additional Information
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
We’re doing work that matters. Help us solve what others can’t.
Seniority level
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Seniority level
Mid-Senior level
Employment type
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Employment type
Full-time
Job function
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Job function
Quality Assurance
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Industries
Software Development
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Sr Principal Verification Engineer employer: Cadence
Contact Detail:
Cadence Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Sr Principal Verification Engineer
✨Tip Number 1
Make sure to showcase your experience with ASIC design and verification in your conversations. Highlight specific projects where you've integrated compute, memory, and interface IP, as this aligns closely with the role's requirements.
✨Tip Number 2
Familiarise yourself with the latest trends in SoC design and verification methodologies. Being able to discuss recent advancements or tools you've used can demonstrate your commitment to staying current in the field.
✨Tip Number 3
Network with professionals in the semiconductor industry, especially those who work at Cadence or similar companies. Engaging in discussions about their experiences can provide valuable insights and potentially lead to referrals.
✨Tip Number 4
Prepare to discuss your proficiency in UVM and EDA tools during interviews. Be ready to share examples of how you've used these tools to improve design simulation and verification processes in past roles.
We think you need these skills to ace Sr Principal Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights relevant experience in ASIC design, integration, and verification. Emphasise your expertise in Verilog/System Verilog and any experience with EDA tools like Cadence and Synopsys.
Craft a Strong Cover Letter: In your cover letter, express your passion for technology and innovation. Mention specific projects or experiences that align with the responsibilities of the Sr Principal Verification Engineer role at Cadence.
Showcase Relevant Skills: Clearly outline your skills in RTL design techniques, UVM for functional verification, and FPGA emulation. Use examples from your past work to demonstrate how these skills have contributed to successful projects.
Highlight Continuous Learning: Mention any recent courses, certifications, or industry trends you’ve followed that relate to the role. This shows your commitment to staying updated in the fast-paced world of technology.
How to prepare for a job interview at Cadence
✨Showcase Your Technical Expertise
As a Sr Principal Verification Engineer, it's crucial to demonstrate your deep understanding of ASIC design and verification. Be prepared to discuss your experience with Verilog/System Verilog, UVM, and EDA tools like Cadence and Synopsys. Highlight specific projects where you've successfully integrated IP and validated SoC designs.
✨Prepare for Problem-Solving Questions
Expect technical questions that assess your problem-solving skills in real-world scenarios. Practice explaining your thought process when debugging SoC reference systems or improving product flows. This will show your analytical abilities and how you approach challenges in the field.
✨Stay Updated on Industry Trends
Cadence values innovation, so be sure to discuss recent trends in electronic design and verification. Familiarise yourself with advancements in machine learning, computer vision, and high-speed interfaces. This knowledge will demonstrate your commitment to staying current and your potential to contribute to the team.
✨Communicate Clearly and Confidently
Effective communication is key in any engineering role. Practice articulating complex technical concepts in a clear and concise manner. During the interview, ensure you listen actively and engage with your interviewers, as this will reflect your collaborative spirit and ability to work within a team.
