At a Glance
- Tasks: Lead complex silicon programs and drive frontend design activities with a talented team.
- Company: Cadence Edinburgh, a leader in innovative chip design.
- Benefits: Competitive salary, flexible working options, and opportunities for professional growth.
- Other info: Join a dynamic team committed to excellence and innovation in chip design.
- Why this job: Shape the future of technology by defining next-generation Chiplets and ensuring high-quality deliverables.
- Qualifications: Experience in RTL design, verification, and a strong understanding of Chiplet architecture.
The predicted salary is between 80000 - 100000 £ per year.
Cadence Edinburgh is seeking a Sr Principal Design Engineer to lead complex silicon programs and drive frontend design activities within a seasoned team. You will collaborate with Chiplet Architecture to define next‑generation Chiplets and oversee the integration of Cadence IP and partner IP across PCIe, UCIe, and related interfaces. You will lead RTL, testbench, formal analysis and verification efforts, ensuring high‑quality deliverables and adherence to ISO‑9001 processes.
Senior Principal Design Engineer: Chiplet IP & RTL Leader in Edinburgh employer: Cadence
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