At a Glance
- Tasks: Lead innovative chip design projects and collaborate with global teams on cutting-edge technology.
- Company: Join Cadence, a leader in electronic design with over 30 years of expertise.
- Benefits: Competitive salary, diverse workplace, and opportunities for professional growth.
- Other info: Dynamic environment with a commitment to diversity and inclusion.
- Why this job: Make a real impact in high-tech markets like AI, automotive, and aerospace.
- Qualifications: 12+ years in microelectronics, strong Verilog RTL design skills, and leadership experience.
The predicted salary is between 80000 - 100000 £ per year.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
Location: Edinburgh, United Kingdom
Reports to: Design Engineering Group Director
Job Overview: The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of High-Tech Markets. The Cadence IP & Chiplet solutions allow our Customers to tackle Silicon product development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence Vision is to deliver industry leading IP & Chiplet solutions to enable our customers to be successful across fast-moving application spaces such as Physical AI, DataCentre and High Performance Computing. The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced Front-End Engineering Team, working with our Global Chiplet team in Europe, India and the USA.
Job Responsibilities:
- Technical leadership of complex Silicon programs consisting of leading-edge IP
- Work closely with our Chiplet Architecture team to define next generation Chiplets
- Integration of Cadence IP Solutions e.g. UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision
- Integration of partner IP Solutions e.g. CPUs, ISP, Silicon Monitors, NoCs
- Hands-on leadership of RTL, Testbench, Formal Analysis and Trial Synthesis activities
- Quality Assurance, via implementation of hierarchical LINT, CDC and release flows
- Planning of activities and milestones for Chiplet Subsystems and System IP development
- Leadership of cross-functional technical meetings with domain leads e.g. Verification, SW
- Support customer pre-sales and post-sales meetings
- Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001
- Represent Cadence by presenting at Industry Conferences such as IEEE, DAC, CDNLive
Job Qualifications:
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 12+ years’ experience in microelectronics/EDA industry
- Experience of Verilog RTL Design essential
- Experience of Metric Driven Verification (MDV) essential
- Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential
- Experience of SoC Architecture and Development essential
- Experience of Technical Team leadership essential
- Excellent oral and written English essential
- Self-motivated with excellent planning, interpersonal, and communication skills
Additional Skills/Preferences:
- Experience of AMBA, PCIe, CXL & UCIe protocols preferred
- Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel: <10%
We’re doing work that matters. Help us solve what others can’t.
Sr Principal Design Engineer (Chiplet Solutions) in Edinburgh employer: Cadence Systems
At Cadence, we pride ourselves on fostering a culture of innovation and collaboration, making us an exceptional employer for those looking to make a significant impact in the technology sector. Located in the vibrant city of Edinburgh, our team enjoys a dynamic work environment that encourages professional growth through hands-on leadership opportunities and engagement with cutting-edge projects in the electronic design space. With a commitment to diversity and inclusion, we empower our employees to thrive while contributing to groundbreaking advancements in high-tech markets.
StudySmarter Expert Advice🤫
We think this is how you could land Sr Principal Design Engineer (Chiplet Solutions) in Edinburgh
✨Tip Number 1
Network like a pro! Reach out to current or former Cadence employees on LinkedIn. A friendly chat can give us insider info and maybe even a referral, which is always a bonus!
✨Tip Number 2
Prepare for the interview by brushing up on your technical skills. Make sure you can discuss your experience with Verilog RTL Design and Metric Driven Verification confidently. We want to see that you can lead complex Silicon programs!
✨Tip Number 3
Showcase your leadership skills! Be ready to share examples of how you've led cross-functional teams in the past. Cadence values innovation and teamwork, so let’s highlight those experiences.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re serious about joining the Cadence team!
We think you need these skills to ace Sr Principal Design Engineer (Chiplet Solutions) in Edinburgh
Some tips for your application 🫡
Tailor Your CV:Make sure your CV is tailored to the Sr Principal Design Engineer role. Highlight your experience in microelectronics and EDA, especially focusing on Verilog RTL Design and Metric Driven Verification. We want to see how your skills align with what we’re looking for!
Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you’re passionate about chiplet solutions and how your background makes you a perfect fit for Cadence. Let us know what excites you about the role and our company.
Showcase Your Leadership Skills:Since this role involves technical leadership, be sure to highlight any relevant experiences where you’ve led teams or projects. We love seeing examples of how you’ve driven success in complex silicon programs!
Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way to ensure your application gets into the right hands. Plus, it shows us you’re serious about joining our team at Cadence!
How to prepare for a job interview at Cadence Systems
✨Know Your Stuff
Make sure you brush up on your technical knowledge, especially around Verilog RTL Design and Metric Driven Verification. Cadence is looking for someone with a solid grasp of these concepts, so be ready to discuss your experience and how it relates to their projects.
✨Showcase Your Leadership Skills
As a Sr Principal Design Engineer, you'll need to demonstrate your leadership abilities. Prepare examples of how you've led teams or projects in the past, particularly in complex Silicon programs. Highlight your experience in cross-functional meetings and how you’ve driven successful outcomes.
✨Understand the Company Vision
Familiarise yourself with Cadence's Intelligent System Design strategy and their focus on Chiplet Solutions. Being able to articulate how your skills align with their vision will show that you're not just interested in the role, but also in contributing to their mission.
✨Prepare for Technical Questions
Expect to face some challenging technical questions during your interview. Review key concepts related to SoC Architecture, LINT, and CDC Analysis. Practising problem-solving scenarios can help you feel more confident when discussing your approach to technical challenges.
