At a Glance
- Tasks: Lead innovative chiplet design projects and collaborate with global teams.
- Company: Join Cadence, a leader in electronic design with over 30 years of expertise.
- Benefits: Competitive salary, diverse workplace, and opportunities for professional growth.
- Other info: Dynamic environment with a commitment to diversity and inclusion.
- Why this job: Make a real impact in high-tech markets like AI, automotive, and aerospace.
- Qualifications: 12+ years in microelectronics, strong Verilog RTL design skills, and leadership experience.
The predicted salary is between 80000 - 100000 £ per year.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
Job Overview: The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of High-Tech Markets. The Cadence IP & Chiplet solutions allow our Customers to tackle Silicon product development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence Vision is to deliver industry leading IP & Chiplet solutions to enable our customers to be successful across fast-moving application spaces such as Physical AI, DataCentre and High Performance Computing. The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced Front-End Engineering Team, working with our Global Chiplet team in Europe, India and the USA.
Job Responsibilities:
- Technical leadership of complex Silicon programs consisting of leading-edge IP
- Work closely with our Chiplet Architecture team to define next generation Chiplets
- Integration of Cadence IP Solutions e.g. UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision
- Integration of partner IP Solutions e.g. CPUs, ISP, Silicon Monitors, NoCs
- Hands-on leadership of RTL, Testbench, Formal Analysis and Trial Synthesis activities
- Quality Assurance, via implementation of hierarchical LINT, CDC and release flows
- Planning of activities and milestones for Chiplet Subsystems and System IP development
- Leadership of cross-functional technical meetings with domain leads e.g. Verification, SW
- Support customer pre-sales and post-sales meetings
- Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001
- Represent Cadence by presenting at Industry Conferences such as IEEE, DAC, CDNLive
Job Qualifications:
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 12+ years’ experience in microelectronics/EDA industry
- Experience of Verilog RTL Design essential
- Experience of Metric Driven Verification (MDV) essential
- Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential
- Experience of SoC Architecture and Development essential
- Experience of Technical Team leadership essential
- Excellent oral and written English essential
- Self-motivated with excellent planning, interpersonal, and communication skills
Additional Skills/Preferences:
- Experience of AMBA, PCIe, CXL & UCIe protocols preferred
- Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Senior Principal Chiplet Design Engineer — IP & SoC Leadership employer: Cadence Design Systems
At Cadence, we foster a dynamic work culture that encourages innovation and leadership, making it an exceptional employer for those in the technology sector. Located in the vibrant city of Edinburgh, our team enjoys a collaborative environment with ample opportunities for professional growth and development, alongside competitive benefits that support work-life balance. Join us to be part of a pioneering company that is shaping the future of electronic design and technology.
StudySmarter Expert Advice🤫
We think this is how you could land Senior Principal Chiplet Design Engineer — IP & SoC Leadership
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, attend meetups, and connect with Cadence employees on LinkedIn. A personal touch can make all the difference when it comes to landing that interview.
✨Tip Number 2
Show off your skills! Prepare a portfolio or a presentation that highlights your past projects and achievements in chiplet design. This will help you stand out during interviews and showcase your expertise.
✨Tip Number 3
Practice makes perfect! Conduct mock interviews with friends or use online platforms to refine your responses. Focus on articulating your experience with Verilog RTL Design and SoC Architecture clearly.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets noticed. Plus, it shows you’re genuinely interested in joining the Cadence team.
We think you need these skills to ace Senior Principal Chiplet Design Engineer — IP & SoC Leadership
Some tips for your application 🫡
Tailor Your CV:Make sure your CV is tailored to the role of Senior Principal Chiplet Design Engineer. Highlight your experience in microelectronics and EDA, and don’t forget to showcase your leadership skills. We want to see how you can make an impact!
Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you're passionate about chiplet solutions and how your background aligns with our vision at Cadence. Let us know what excites you about this opportunity!
Showcase Relevant Projects:Include specific projects that demonstrate your expertise in Verilog RTL Design and SoC Architecture. We love seeing real-world applications of your skills, so don’t hold back on the details!
Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy!
How to prepare for a job interview at Cadence Design Systems
✨Know Your Chiplets
Make sure you brush up on the latest trends and technologies in chiplet design. Familiarise yourself with Cadence's specific IP solutions like UCIe and PCIe, as well as any relevant protocols. This will show your genuine interest and understanding of the role.
✨Showcase Your Leadership Skills
As a Senior Principal Design Engineer, you'll need to demonstrate your technical leadership experience. Prepare examples from your past roles where you've led complex projects or teams, especially in microelectronics or EDA. Highlight how you managed cross-functional teams and drove successful outcomes.
✨Prepare for Technical Questions
Expect in-depth technical questions related to Verilog RTL design and Metric Driven Verification. Brush up on your knowledge of front-end design tools and be ready to discuss your hands-on experience with LINT, synthesis, and CDC analysis. Practice articulating your thought process clearly.
✨Engage with the Interviewers
Interviews are a two-way street! Prepare thoughtful questions about Cadence's vision for chiplet solutions and how they integrate with customer needs. This not only shows your enthusiasm but also helps you gauge if the company aligns with your career goals.
