At a Glance
- Tasks: Lead the development of cutting-edge verification tools and methodologies in AI and Machine Learning.
- Company: Join Cadence, a leader in electronic design with over 30 years of innovation.
- Benefits: Enjoy competitive salary, 25 days holiday, private medical plans, and gym subsidies.
- Other info: Be part of a diverse team committed to innovation and community engagement.
- Why this job: Make a real impact in technology while working with top-tier teams on exciting projects.
- Qualifications: Degree in Electrical/Electronic Engineering and 4+ years in microelectronics/EDA required.
The predicted salary is between 60000 - 75000 € per year.
Locations: Edinburgh
Time Type: Full time
Posted on: Posted 16 Days Ago
Job Requisition ID: R54228
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
Reports to: Design Engineering Group Director
Job Overview: The Cadence Silicon Systems Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets. As a member of the Central Engineering Team within SSG, you will be responsible for defining and supporting the adoption of cutting-edge verification tools and methodologies with a focus on AI and Machine Learning. You will have a horizontal role working with multiple projects and teams to accelerate adoption of latest verification best practices. The Lead Verification Engineer will be based in Edinburgh, Scotland as part of an experienced digital design and verification IP team.
Job Responsibilities:
- Develop and support adoption of generative AI tools to create and update, UVM and Formal verification environments
- Develop methodology guidance and end to end flows to ensure AI tools used in a consistent, efficient and predictable way
- Develop and roll out solutions that reduce verification debug time
- Automate documentation checking to improve quality and consistency
- Build tools and processes to support verification planning
- Optimise UVM regressions through improved automation and machine learning
- Maintain and develop best practices for Functional Safety Verification, Gate Level Simulation and Low Power Verification
- Maintain and improve design review checklists and quality documentation
Job qualifications and required skills:
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 4+ years experience in the microelectronics/EDA industry
- Proficiency in System Verilog and assertions
- Hands-on experience with Metric Driven Verification (MDV)
- Strong knowledge of constrained-random verification techniques (e.g. UVM)
- Excellent spoken and written English
- Self-motivated, with strong planning, interpersonal, and communication skills
Additional Skills/Preferences:
- Formal verification experience and related applications
- Proficiency with scripting languages (e.g. Python)
- Knowledge of AI agent development (tools, concepts, and infrastructure)
- Methodology development and change management experience
- Familiarity with front-end design tools (e.g. LINT, CDC analysis)
- Exposure to quality processes and standards (e.g. ISO 9001, ISO 26262)
Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Check what we can offer you:
- Competitive salary
- 25 days holiday per year
- Private Medical and Dental plans, Income Protection and Life Insurance
- Group Personal Pension Plan
- Cycle to work scheme and gym subsidy
- 5 days paid time to volunteer to give back to our communities
- Employee Stock Purchase Plan
- The opportunity to work for a Great Place to Work (C)& Fortune 100 organization
Travel:
Lead Digital Verification Engineer employer: Cadence Design Systems
At Cadence, we foster a culture of innovation and leadership, making it an exceptional employer for those looking to make a significant impact in technology. Located in the vibrant city of Edinburgh, our team enjoys a supportive work environment that prioritises employee growth through diverse opportunities, competitive benefits, and a commitment to community engagement. With a focus on cutting-edge technologies and methodologies, we empower our employees to excel in their careers while contributing to groundbreaking advancements in electronic design.
StudySmarter Expert Advice🤫
We think this is how you could land Lead Digital Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to folks in the industry, attend meetups, and connect with current employees at Cadence. A friendly chat can sometimes lead to opportunities that aren’t even advertised!
✨Tip Number 2
Show off your skills! If you’ve got a portfolio or any projects that highlight your expertise in digital verification, make sure to share them during interviews. It’s a great way to demonstrate what you can bring to the table.
✨Tip Number 3
Prepare for those tricky questions! Brush up on your knowledge of AI and machine learning as they’re key in this role. Think about how you can apply these concepts in real-world scenarios and be ready to discuss them.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining the Cadence team.
We think you need these skills to ace Lead Digital Verification Engineer
Some tips for your application 🫡
Tailor Your CV:Make sure your CV is tailored to the Lead Digital Verification Engineer role. Highlight your experience with AI tools, UVM, and any relevant projects that showcase your skills in verification methodologies.
Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you're passionate about this role and how your background aligns with Cadence's mission. Don’t forget to mention your experience in the microelectronics/EDA industry.
Showcase Your Skills:In your application, be sure to highlight your proficiency in System Verilog and any scripting languages like Python. Mention specific examples of how you've used these skills in past projects to solve problems or improve processes.
Apply Through Our Website:We encourage you to apply through our website for the best chance of getting noticed. It’s straightforward and ensures your application goes directly to the right team. Plus, we love seeing candidates who take the initiative!
How to prepare for a job interview at Cadence Design Systems
✨Know Your Tech Inside Out
Make sure you brush up on your knowledge of System Verilog, UVM, and AI tools. Be ready to discuss how you've applied these in past projects, as well as any challenges you've faced and how you overcame them.
✨Showcase Your Problem-Solving Skills
Prepare examples that highlight your ability to develop methodologies and improve verification processes. Think about specific instances where you've reduced debug time or optimised regression flows, and be ready to share those stories.
✨Communicate Clearly and Confidently
Since excellent communication is key for this role, practice explaining complex technical concepts in simple terms. This will not only demonstrate your expertise but also your ability to work with cross-functional teams.
✨Ask Insightful Questions
Prepare thoughtful questions about Cadence's approach to AI in verification and their future projects. This shows your genuine interest in the company and helps you assess if it's the right fit for you.
