At a Glance
- Tasks: Lead innovative chiplet design projects and collaborate with global teams.
- Company: Join Cadence, a leader in electronic design with over 30 years of expertise.
- Benefits: Competitive salary, diverse workplace, and opportunities for professional growth.
- Other info: Dynamic environment with a commitment to diversity and inclusion.
- Why this job: Make a real impact in high-tech markets like AI, automotive, and aerospace.
- Qualifications: 12+ years in microelectronics, strong Verilog RTL design skills, and leadership experience.
The predicted salary is between 80000 - 100000 £ per year.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
Job Overview: The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of High-Tech Markets. The Cadence IP & Chiplet solutions allow our Customers to tackle Silicon product development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence Vision is to deliver industry leading IP & Chiplet solutions to enable our customers to be successful across fast-moving application spaces such as Physical AI, DataCentre and High Performance Computing. The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced Front-End Engineering Team, working with our Global Chiplet team in Europe, India and the USA.
Job Responsibilities:
- Technical leadership of complex Silicon programs consisting of leading-edge IP
- Work closely with our Chiplet Architecture team to define next generation Chiplets
- Integration of Cadence IP Solutions e.g. UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision
- Integration of partner IP Solutions e.g. CPUs, ISP, Silicon Monitors, NoCs
- Hands-on leadership of RTL, Testbench, Formal Analysis and Trial Synthesis activities
- Quality Assurance, via implementation of hierarchical LINT, CDC and release flows
- Planning of activities and milestones for Chiplet Subsystems and System IP development
- Leadership of cross-functional technical meetings with domain leads e.g. Verification, SW
- Support customer pre-sales and post-sales meetings
- Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001
- Represent Cadence by presenting at Industry Conferences such as IEEE, DAC, CDNLive
Job Qualifications:
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 12+ years’ experience in microelectronics/EDA industry
- Experience of Verilog RTL Design essential
- Experience of Metric Driven Verification (MDV) essential
- Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential
- Experience of SoC Architecture and Development essential
- Experience of Technical Team leadership essential
- Excellent oral and written English essential
- Self-motivated with excellent planning, interpersonal, and communication skills
Additional Skills/Preferences:
- Experience of AMBA, PCIe, CXL & UCIe protocols preferred
- Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Senior Principal Chiplet Design Engineer — IP & SoC Leadership in Edinburgh employer: Cadence Design Systems
At Cadence, we foster a dynamic work culture that encourages innovation and leadership, making it an exceptional employer for those in the technology sector. Located in the vibrant city of Edinburgh, our team enjoys a collaborative environment with ample opportunities for professional growth and development, while contributing to cutting-edge projects in the high-tech industry. With a commitment to diversity and inclusion, we empower our employees to make a meaningful impact on the world of technology.
StudySmarter Expert Advice🤫
We think this is how you could land Senior Principal Chiplet Design Engineer — IP & SoC Leadership in Edinburgh
✨Network Like a Pro
Get out there and connect with people in the industry! Attend tech meetups, conferences, or even online webinars. You never know who might have the inside scoop on job openings or can put in a good word for you.
✨Show Off Your Skills
When you get the chance to chat with potential employers, don’t hold back! Share your past projects and experiences that relate to chiplet design and IP solutions. Let them see how you can make an impact at Cadence.
✨Tailor Your Approach
Do your homework on Cadence and their current projects. When you reach out, mention specific technologies or challenges they’re facing. This shows you’re genuinely interested and ready to contribute from day one.
✨Apply Through Our Website
Don’t forget to apply directly through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re proactive and really want to be part of the Cadence team.
We think you need these skills to ace Senior Principal Chiplet Design Engineer — IP & SoC Leadership in Edinburgh
Some tips for your application 🫡
Tailor Your CV:Make sure your CV is tailored to the role of Senior Principal Chiplet Design Engineer. Highlight your experience in microelectronics and EDA, and don’t forget to showcase your leadership skills. We want to see how you can make an impact!
Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you're passionate about chiplet solutions and how your background aligns with our vision at Cadence. Let us know what excites you about this opportunity!
Showcase Relevant Projects:Include specific projects that demonstrate your expertise in Verilog RTL Design and SoC Architecture. We love seeing real-world applications of your skills, so don’t hold back on the details!
Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy to do!
How to prepare for a job interview at Cadence Design Systems
✨Know Your Chiplet Stuff
Make sure you brush up on your knowledge of chiplet design and integration. Familiarise yourself with the latest trends in IP solutions, especially UCIe and PCIe. Being able to discuss these topics confidently will show that you're not just a candidate, but a potential leader in the field.
✨Showcase Your Leadership Skills
Since this role involves technical leadership, be prepared to share examples of how you've led teams or projects in the past. Highlight your experience in cross-functional meetings and how you've driven successful outcomes. This will demonstrate your capability to lead at Cadence.
✨Prepare for Technical Questions
Expect in-depth technical questions related to Verilog RTL design and Metric Driven Verification. Brush up on your front-end design tools knowledge, including LINT and CDC analysis. Practising these concepts will help you answer confidently and accurately during the interview.
✨Engage with the Interviewers
Don't forget that interviews are a two-way street! Prepare thoughtful questions about Cadence's projects and future directions in chiplet technology. Engaging with the interviewers shows your genuine interest in the company and the role, making you a memorable candidate.
