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- Tasks: Develop and maintain verification environments for cutting-edge FPGA and ASIC designs.
- Company: Join a leading global technology firm with a focus on innovation.
- Benefits: Competitive salary, flexible work options, and opportunities for professional growth.
- Why this job: Make an impact in real-time systems and enhance the EDA ecosystem.
- Qualifications: 2+ years in FPGA/ASIC verification and strong SystemVerilog skills required.
- Other info: Collaborative team environment with a focus on tool improvement and open-source contributions.
The predicted salary is between 36000 - 60000 £ per year.
A leading global technology firm is seeking a Senior Design Verification Engineer to work on high-performance FPGA and ASIC systems used in ultra-low-latency, real-time environments. This role focuses on building robust verification frameworks to ensure the correctness, reliability, and performance of complex hardware designs. You’ll design and own verification environments, work closely with RTL designers on rapid bring-up and debugging, and contribute to both internal and open-source tooling. The team values engineers who are not only strong verifiers but also enjoy improving tools, workflows, and the broader EDA ecosystem. No domain-specific (e.g., finance) experience is required.
Key responsibilities
- Develop testbenches, tests, and verification environments for FPGA/ASIC designs
- Create and maintain detailed verification plans
- Debug and root-cause complex RTL issues
- Collaborate closely with hardware designers on new and existing projects
- Manage test suites, coverage, and CI infrastructure
- Contribute to internal tools and open-source verification projects
Key requirements
- 2+ years’ experience in FPGA or ASIC functional verification
- Strong SystemVerilog skills (UVM or similar frameworks)
- Experience with functional and code coverage
- Proficiency in Python; C++ a plus
- Comfortable working in a Linux environment
- Familiarity with Verilator and/or Cocotb is advantageous
- Degree in Electrical Engineering, Computer Science, or related field
Senior Design Verification Engineer employer: Berkeley Square - Talent Specialists in IT & Engineering
Contact Detail:
Berkeley Square - Talent Specialists in IT & Engineering Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior Design Verification Engineer
✨Tip Number 1
Network like a pro! Reach out to your connections in the tech industry, especially those who work with FPGA and ASIC systems. A friendly chat can lead to insider info about job openings that aren’t even advertised yet.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your verification environments and any open-source contributions. This is your chance to demonstrate your expertise in SystemVerilog and Python, making you stand out to potential employers.
✨Tip Number 3
Prepare for interviews by brushing up on debugging techniques and verification strategies. Be ready to discuss how you've tackled complex RTL issues in the past. We want to see your problem-solving skills in action!
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets noticed. Plus, we love seeing candidates who are proactive and engaged with our company.
We think you need these skills to ace Senior Design Verification Engineer
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience with FPGA and ASIC verification. We want to see how your skills align with the role, so don’t be shy about showcasing your SystemVerilog expertise and any relevant projects you've worked on.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about design verification and how you can contribute to our team. We love seeing candidates who are excited about improving tools and workflows, so let that enthusiasm show!
Showcase Your Projects: If you've worked on any open-source projects or internal tools, make sure to mention them. We value collaboration and innovation, so sharing your experiences in these areas can really set you apart from other applicants.
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it gives you a chance to explore more about our company culture and values!
How to prepare for a job interview at Berkeley Square - Talent Specialists in IT & Engineering
✨Know Your Tech Inside Out
Make sure you brush up on your SystemVerilog skills and be ready to discuss UVM or similar frameworks. Familiarity with FPGA/ASIC design principles is crucial, so prepare to talk about your past experiences and how they relate to the role.
✨Show Off Your Problem-Solving Skills
Be prepared to tackle some technical questions or scenarios during the interview. Think of examples where you've debugged complex RTL issues or improved verification environments. This will showcase your analytical skills and hands-on experience.
✨Collaboration is Key
Since the role involves working closely with hardware designers, highlight your teamwork experiences. Share specific instances where you collaborated on projects, especially in a fast-paced environment, to demonstrate your ability to communicate effectively.
✨Contribute to the Bigger Picture
Express your enthusiasm for contributing to both internal tools and open-source projects. Discuss any relevant projects you've worked on that align with this, as it shows you're not just a strong verifier but also someone who cares about improving the broader EDA ecosystem.