Sr. Formal Verification Engineer

Sr. Formal Verification Engineer

Full-Time 48000 - 72000 £ / year (est.) No working from home possible
Baya Systems

At a Glance

  • Tasks: Develop and implement formal verification test plans to ensure design correctness.
  • Company: Baya Systems, a leader in computer hardware and semiconductor manufacturing.
  • Benefits: Full-time position with competitive salary and opportunities for professional growth.
  • Other info: Collaborative environment with opportunities for innovation and career advancement.
  • Why this job: Join a dynamic team and make a significant impact on cutting-edge technology.
  • Qualifications: 6-7 years of experience in formal verification and strong skills in System Verilog.

The predicted salary is between 48000 - 72000 £ per year.

Baya Systems is seeking an experienced Sr. Formal Verification specialist to join the DV team in England, United Kingdom. This position will be onsite at a strategic office location yet to be determined. Overall, we are looking for at least 6/7 years of industry experience.

Responsibilities

  • Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.
  • Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.
  • Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.
  • Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.
  • Develop and maintain scripts to enhance FV productivity and streamline verification processes.
  • Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.
  • Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, and area (PPA) metrics based on formal analysis feedback.

Qualifications

  • Strong proficiency in System Verilog/Verilog.
  • Good scripting abilities with Python or Perl.

Preferred Experience

  • Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
  • Experience with both bug hunting and static proof verification techniques.
  • Familiarity with automating formal verification workflows within a CI/CD environment.

For those interested, please apply to the job posting below or contact: Manager, Talent Acquisition

Job details

  • Seniority level: Mid-Senior level
  • Employment type: Full-time
  • Job function: Engineering and Other
  • Industries: Computer Hardware Manufacturing, Semiconductor Manufacturing, and Software Development
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Sr. Formal Verification Engineer employer: Baya Systems

Baya Systems is an exceptional employer, offering a dynamic work environment in the heart of England, where innovation meets collaboration. With a strong focus on employee growth, we provide ample opportunities for professional development and skill enhancement, particularly in cutting-edge formal verification technologies. Our inclusive culture fosters teamwork and creativity, ensuring that every team member's contributions are valued and recognised, making it a rewarding place to advance your career.

Baya Systems

Contact Details:

Baya Systems Recruitment Team

StudySmarter Expert Advice🤫

We think this is how you could land Sr. Formal Verification Engineer

Tip Number 1

Network like a pro! Reach out to your connections in the industry, especially those who work at Baya Systems or similar companies. A friendly chat can sometimes lead to insider info about job openings or even a referral.

Tip Number 2

Prepare for interviews by brushing up on your technical skills and understanding the latest trends in formal verification. We recommend practising common interview questions and scenarios related to System Verilog and EDA tools.

Tip Number 3

Showcase your projects! If you've worked on relevant formal verification projects, be ready to discuss them in detail. We love seeing how you’ve applied your skills in real-world situations.

Tip Number 4

Don’t forget to apply through our website! It’s the best way to ensure your application gets noticed. Plus, it shows you’re genuinely interested in joining our team at Baya Systems.

We think you need these skills to ace Sr. Formal Verification Engineer

Formal Verification
Test Plan Development
Micro-architecture Specification
Logic Component Identification
Assertion-based Model Checking
Complexity Reduction Techniques
EDA Tools

Some tips for your application 🫡

Tailor Your CV:Make sure your CV is tailored to highlight your experience in formal verification and relevant tools. We want to see how your skills align with the job description, so don’t hold back on showcasing your expertise!

Craft a Compelling Cover Letter:Your cover letter is your chance to shine! Use it to explain why you’re passionate about formal verification and how your background makes you a perfect fit for our team. Keep it engaging and personal – we love to see your personality!

Showcase Your Projects:If you've worked on any projects related to formal verification, make sure to mention them! We’re interested in seeing real examples of your work, especially if they involve tools like Synopsys VCFormal or Cadence JasperGold.

Apply Through Our Website:We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy – just follow the prompts!

How to prepare for a job interview at Baya Systems

Know Your Formal Verification Inside Out

Make sure you brush up on your formal verification knowledge, especially around the tools mentioned in the job description like Synopsys VCFormal and Cadence JasperGold. Be ready to discuss your hands-on experience with these tools and how you've used them to tackle complex verification challenges.

Showcase Your Scripting Skills

Since scripting is a key part of the role, prepare to talk about your experience with Python or Perl. Bring examples of scripts you've developed that enhanced FV productivity or streamlined verification processes, and be ready to explain the impact they had on your projects.

Prepare for Technical Questions

Expect technical questions that dive deep into your understanding of System Verilog/Verilog and formal verification methodologies. Practise explaining complex concepts clearly and concisely, as this will demonstrate your expertise and communication skills.

Collaborative Mindset is Key

Baya Systems values collaboration, so be prepared to discuss how you've worked with design teams in the past. Share specific examples of how you contributed to design reviews and optimised design quality based on formal analysis feedback, highlighting your teamwork and problem-solving abilities.