Sr. Formal Verification Engineer

Sr. Formal Verification Engineer

Full-Time 48000 - 72000 £ / year (est.) On-site
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At a Glance

  • Tasks: Develop and implement formal verification test plans to ensure design correctness.
  • Company: Baya Systems, a leader in computer hardware and semiconductor manufacturing.
  • Benefits: Full-time position with competitive salary and opportunities for professional growth.
  • Other info: Collaborative environment with opportunities for innovation and career advancement.
  • Why this job: Join a dynamic team and make a significant impact on cutting-edge technology.
  • Qualifications: 6-7 years of experience in formal verification and strong skills in System Verilog.

The predicted salary is between 48000 - 72000 £ per year.

Baya Systems is seeking an experienced Sr. Formal Verification specialist to join the DV team in England, United Kingdom. This position will be onsite at a strategic office location yet to be determined. Overall, we are looking for at least 6/7 years of industry experience.

Responsibilities

  • Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.
  • Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.
  • Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.
  • Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.
  • Develop and maintain scripts to enhance FV productivity and streamline verification processes.
  • Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.
  • Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, and area (PPA) metrics based on formal analysis feedback.

Qualifications

  • Strong proficiency in System Verilog/Verilog.
  • Good scripting abilities with Python or Perl.

Preferred Experience

  • Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
  • Experience with both bug hunting and static proof verification techniques.
  • Familiarity with automating formal verification workflows within a CI/CD environment.

For those interested, please apply to the job posting below or contact: Manager, Talent Acquisition

Job details

  • Seniority level: Mid-Senior level
  • Employment type: Full-time
  • Job function: Engineering and Other
  • Industries: Computer Hardware Manufacturing, Semiconductor Manufacturing, and Software Development

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Sr. Formal Verification Engineer employer: Baya Systems

Baya Systems is an exceptional employer that fosters a dynamic and innovative work culture in Newtown, UK. With a focus on employee growth, we offer extensive training opportunities and performance incentives, ensuring our team thrives in a fast-paced startup environment. Join us to be part of a collaborative team dedicated to solving customer challenges in the semiconductor industry while enjoying comprehensive health benefits.

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Contact Details:

Baya Systems Recruitment Team

StudySmarter Expert Advice🤫

We think this is how you could land Sr. Formal Verification Engineer

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We think you need these skills to ace Sr. Formal Verification Engineer

Formal Verification
Test Plan Development
Micro-architecture Specification
Logic Component Identification
Assertion-based Model Checking
Complexity Reduction Techniques
EDA Tools

Some tips for your application 🫡

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