Baya Systems is seeking a seasoned Design Verification engineer to design and implement testbenches for complex IPs, chips and interconnects. You will create test plans and write UVM/SystemVerilog code to verify multi-chiplet interconnects and NoCs.
You will collaborate with software and design teams, debug failures, drive coverage, and contribute to the technology portfolio. Requirements include 8+ years in verification, Verilog/SystemVerilog, UVM, Python, and AMBA/CHI protocol knowledge.
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Senior DV Engineer: UVM Testbenches for SoC IPs (Equity) employer: Baya Systems
Baya Systems is an exceptional employer located in the vibrant tech hub of Cambridge, UK, offering a dynamic work culture that fosters innovation and collaboration. Employees benefit from comprehensive professional development opportunities, competitive compensation, and a supportive environment that encourages creativity and growth. Join us to be part of a forward-thinking team dedicated to shaping cutting-edge technology in a city renowned for its rich academic and technological heritage.
