Find a job 
Featured Companies 
Featured Universities 
For Companies At a Glance
- Tasks: Develop and implement formal verification test plans to ensure design correctness.
- Company: Join Baya Systems, a leader in computer hardware and semiconductor manufacturing.
- Benefits: Full-time position with competitive salary and opportunities for professional growth.
- Why this job: Make a real impact in cutting-edge technology and collaborate with talented teams.
- Qualifications: 6-7 years of experience in formal verification and strong skills in System Verilog.
- Other info: Dynamic work environment with opportunities for innovation and career advancement.
The predicted salary is between 48000 - 72000 £ per year.
Baya Systems is seeking an experienced Sr. Formal Verification specialist to join the DV team in England, United Kingdom. This position will be onsite at a strategic office location yet to be determined. Overall, we are looking for at least 6/7 years of industry experience.
Responsibilities
- Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.
- Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.
- Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.
- Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.
- Develop and maintain scripts to enhance FV productivity and streamline verification processes.
- Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.
- Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, and area (PPA) metrics based on formal analysis feedback.
Qualifications
- Strong proficiency in System Verilog/Verilog.
- Good scripting abilities with Python or Perl.
Preferred Experience
- Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
- Experience with both bug hunting and static proof verification techniques.
- Familiarity with automating formal verification workflows within a CI/CD environment.
Sr. Formal Verification Engineer in London employer: Baya Systems
Contact Detail:
Baya Systems Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Sr. Formal Verification Engineer in London
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, especially those who work at Baya Systems or similar companies. A friendly chat can sometimes lead to insider info about job openings or even a referral.
✨Tip Number 2
Prepare for interviews by brushing up on your technical skills and understanding the latest trends in formal verification. We recommend practising common interview questions and scenarios related to System Verilog and EDA tools.
✨Tip Number 3
Showcase your projects! If you've worked on relevant formal verification projects, be ready to discuss them in detail. We love seeing how you’ve applied your skills in real-world situations.
✨Tip Number 4
Don’t forget to apply through our website! It’s the best way to ensure your application gets seen by the right people. Plus, it shows you’re genuinely interested in joining the team at Baya Systems.
We think you need these skills to ace Sr. Formal Verification Engineer in London
Some tips for your application 🫡
Tailor Your CV: Make sure your CV highlights your experience in formal verification and relevant tools like System Verilog or Python. We want to see how your skills match the job description, so don’t be shy about showcasing your achievements!
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you’re passionate about formal verification and how your background makes you a perfect fit for our team. Keep it engaging and personal – we love to see your personality!
Showcase Relevant Projects: If you've worked on any projects that involved formal verification or related technologies, make sure to mention them. We’re keen to see real-world applications of your skills, so don’t hold back on the details!
Apply Through Our Website: We encourage you to apply directly through our website. It’s the best way for us to receive your application and ensures you’re considered for the role. Plus, it’s super easy – just follow the prompts!
How to prepare for a job interview at Baya Systems
✨Know Your Formal Verification Inside Out
Make sure you brush up on your formal verification knowledge, especially around the tools mentioned like Synopsys VCFormal and Cadence JasperGold. Be ready to discuss specific projects where you've implemented these tools and how they helped in bug detection or proof convergence.
✨Showcase Your Scripting Skills
Since scripting is a key part of the role, prepare to talk about your experience with Python or Perl. Bring examples of scripts you've developed that enhanced FV productivity or streamlined verification processes, and be ready to explain the impact they had on your previous projects.
✨Collaborate and Communicate
This role involves working closely with design teams, so highlight your collaboration skills. Think of instances where you participated in design reviews or helped refine micro-architecture specifications, and be prepared to discuss how you communicated complex ideas effectively.
✨Prepare for Technical Questions
Expect technical questions that test your understanding of logic components and micro-architectural properties. Review common corner-case bugs and complexity reduction techniques, and be ready to demonstrate your problem-solving approach during the interview.
