Design Verification Engineer

• Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design teams test plans, failure debug, coverage, etc.
  We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions, BS, MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification
• Proficiency in Verilog, SystemVerilog
• Familiarity with industry-standard EDA tools for simulation and debug
• Deep experience with UVM-based testbenches
• Experience with modern programming languages like Python
• Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
• Understanding of Arm CHI protocol is a plus
• Experience on working with IP's for caches, cache coherency, memory subsystems, interconnects, and NoC's
• Experience with formal verification techniques, emulation platforms is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills
  Salary commensurate with experience
• Performance incentives
• Comprehensive medical, dental, and vision benefits
• 401(k) retirement plan
• Equity

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