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- Tasks: Shape technology by creating test plans and writing UVM/SystemVerilog code for complex IPs.
- Company: Join a leading tech firm in Cambridge with a hybrid work model.
- Benefits: Enjoy competitive salary, flexible working, and opportunities for professional growth.
- Other info: Dynamic team environment with excellent career advancement opportunities.
- Why this job: Make a real impact in cutting-edge hardware verification and collaborate with top engineers.
- Qualifications: 8+ years in verification, strong coding skills in Verilog/SystemVerilog, and problem-solving abilities.
The predicted salary is between 60000 - 80000 £ per year.
Location: Cambridge, England, United Kingdom (Hybrid possible inside the UK)
About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.
Responsibilities:
- Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems.
- Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards.
- Collaborate with software teams to define and implement configurable testbenches.
- Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.
Qualifications:
- BS/MS in Electrical Engineering, Computer Engineering or Computer Science.
- 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification.
- Proficiency in Verilog, SystemVerilog.
- Familiarity with industry-standard EDA tools for simulation and debug.
- Deep experience with UVM-based testbenches.
- Experience with modern programming languages like Python.
- Knowledge of ARM AMBA protocols such as AXI, APB, and AHB.
- Understanding of ARM CHI protocol is a plus.
- Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs.
- Experience with formal verification techniques, emulation platforms is a plus.
- Excellent problem-solving skills and attention to detail.
- Strong communication and collaboration skills.
Senior Engineer, Design Verification Engineering in Cambridge employer: Baya Systems
Contact Detail:
Baya Systems Recruiting Team
StudySmarter Expert Advice 🤫
We think this is how you could land Senior Engineer, Design Verification Engineering in Cambridge
✨Tip Number 1
Network like a pro! Reach out to your connections in the industry, attend meetups, and engage in online forums. You never know who might have the inside scoop on job openings or can refer you directly.
✨Tip Number 2
Show off your skills! Create a portfolio showcasing your best work in design verification. Include examples of testbenches you've built or complex IPs you've worked on. This will give potential employers a taste of what you can bring to the table.
✨Tip Number 3
Prepare for interviews by brushing up on your technical knowledge. Be ready to discuss UVM/SystemVerilog code and your experience with EDA tools. Practising common interview questions can also help you feel more confident.
✨Tip Number 4
Don't forget to apply through our website! We love seeing applications come directly from candidates who are excited about joining us. Tailor your application to highlight your relevant experience and how you can contribute to our team.
We think you need these skills to ace Senior Engineer, Design Verification Engineering in Cambridge
Some tips for your application 🫡
Tailor Your CV: Make sure your CV is tailored to the Senior Hardware Verification Engineer role. Highlight your experience with UVM/SystemVerilog and any relevant projects that showcase your skills in building testbenches and writing test sequences.
Craft a Compelling Cover Letter: Your cover letter is your chance to shine! Use it to explain why you're the perfect fit for our team. Mention specific experiences that align with the responsibilities listed in the job description, especially your collaboration with design and architecture teams.
Showcase Your Technical Skills: Don’t forget to emphasise your technical expertise! Include your proficiency in Verilog, SystemVerilog, and any familiarity with EDA tools. If you have experience with ARM protocols or formal verification techniques, make sure to mention those too!
Apply Through Our Website: We encourage you to apply through our website for a smoother application process. It helps us keep track of your application and ensures you don’t miss out on any important updates from us!
How to prepare for a job interview at Baya Systems
✨Know Your Tech Inside Out
Make sure you brush up on your knowledge of Verilog, SystemVerilog, and UVM. Be ready to discuss specific projects where you've built testbenches or written test sequences. This will show that you not only understand the theory but have practical experience too.
✨Collaborate Like a Pro
Since the role involves working closely with design and architecture teams, be prepared to talk about how you've successfully collaborated in the past. Share examples of how you’ve created test plans or debugged failures as part of a team. This will highlight your teamwork skills.
✨Show Off Your Problem-Solving Skills
Prepare to discuss challenging verification problems you've faced and how you solved them. Use specific examples that demonstrate your analytical thinking and attention to detail. This is crucial for a Senior Engineer role.
✨Familiarise Yourself with Industry Standards
Make sure you know the ARM AMBA protocols and any other relevant standards. Being able to discuss these in detail will set you apart from other candidates. It shows you're not just technically proficient but also aware of industry trends.